VSX-AX5Ai-S
158
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Function
Miscellaneous Pins
No.
Pin Name
I/O
Pin Function
64
DISABLE_IFn
I
Interface disable. When asserted, the interfaces are put into a high-Z state. Interfaces include: ex-CPU,
HSDI, GPIO, and WTCH_DG_TMRn.
62
HPS
I
Host power status. This indicates the power status of the external system to iceLynx-Micro. A rising edge
indicates the system CPU has been turned ON. (The internal ARM must wake up.) A falling edge
indicates the system CPU has been turned OFF. (The internal ARM decides if power down is
necessary.)
63
LOW_PWR_RDY
O
Output to system to indicate iceLynx-Micro is ready to go into a low power state. The ARM and
WTCH_DG_TMRn control this pin.
88
WTCH_DG_TMRn
O
Watch dog timer (for the ARM). iceLynx-Micro hardware asserts this pin whenever ARM software has
not updated the Timer2 register within the allowed time period.
60
RESET_ARMn
I
ARM reset. This signal resets the internal ARM processor.
59
RESETn
I
Device reset. This signal resets all logic.This includes the PHY,link core, memory, the ARM, and random
logic.
External CPU Interface Pins
Regulator Pins
Power and Ground Pins
No.
Pin Name
I/O
Pin Function
1,21,55,76,
102,117,131,
146,162,176
VSS
−
Digital ground
24,27,35,45
AGND
−
Analog ground
54
PLL_GND
−
PLL ground
4,20,56,75,
101,116,130,
145,161,175
VDD
−
Digital power supply. Must be set to 3.3-V nominal.
23,28,32,41,48 AVDD
−
Analog power supply. Must be set to 3.3-V nominal.
51
PLL_VDD
−
PLL power supply. Must be set to 3.3-V nominal.
No.
Pin Name
I/O
Pin Function
73
REG_ENn
I
Internal regulator enable. The iceLynx-Micro core voltage is 1.8 V. Internal regulators are used to
regulate the 3.3-V VDD inputs to 1.8 V. This pin enables the regulators.
74
REG_OUT0
O
1.8-V regulator output. This pin must be connected to ground using a 0.1-
µ
F capacitor.
115 REG_OUT1
O
1.8-V regulator output. This pin must be connected to ground using a 0.1-
µ
F capacitor.
160 REG_OUT2
O
1.8-V regulator output. This pin must be connected to ground using a 0.1-
µ
F capacitor.
No.
Pin Name
I/O
Pin Function
95
MCIF_ACKz
I/O
MCIF acknowledge pin. Default active low. iceLynx-Micro asserts this signal if it has completed the MCIF
request. This signal is driven when chip select (CS) is asserted. This signal is used for the following
modes:
• 68000 + wait I/O access
• I/O Type-3 MPC850
120 MCIF_ADDR1
I
MCIF address 1 pin. This data pin is the least significant bit of the MCIF address bus.
MCIF_ADDR0 is internally grounded. Only 16-bit addressing is allowed. MCIF_ADDR1 must be
connected to the Address1 signal of the system CPU.
