VSX-AX5Ai-S
170
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Function
No.
Pin Name
I/O
Function
1
V
DD2
−
ADC and DAC analog power supply
2
BIAS
−
ADC bias voltage.
Stabilize by attaching a 0.01
µ
F capacitor.
3
VRT
−
ADC input range D upper limit voltage.
Stabilize by attaching a 0.01
µ
F capacitor.
4
NC
−
Non connection
5
AIN
I
ADC input. Inputs 1.0 Vp-p video signal.
Sync tip clamp is performed.
6
VRB
−
ADC input range D lower limit voltage.
Stabilize by attaching a 0.01
µ
F capacitor.
7
V
DD3
−
ADC and DAC logic power supply
8
V
SS2
−
Logic and internal DRAM GND (digital)
9
NC
−
Non connection
10
V
DD4
−
Internal DRAM power supply
11
SDA
−
I
2
C BUS SDA
12
SCL
−
I
2
C BUS SCL
13
TEST
I
Shipment test mode switch or I
2
C bus setting reset pin.
When High, test mode, setting all I
2
C bus settings to 0.
Hold High for at least 100
µ
s. Send I
2
C bus settings when this pin is Low.
14
KILLER
I
Y signal comb function ON / OFF switch.
When High, comb OFF. When Low, comb ON.
When [data 3 : bit 0] is 1, used as vertical edge enhancement circuit ON / OFF switch.
15
CKIN
I
Clock input pin. This pin put a sine wave which is locked to the frequency of the burst signal in the input
video signal.
Amplitude is 300 mV p-p to 2 Vp-p.
Input as high an amplitude as possible without affecting peripheral circuits.
16
NC
−
Non connection
17
FIL
O
Connect the APC filter in the 8 fsc PLL circuit
18
V
DD1
−
PLL power supply
19
V
SS1
−
ADC, DAC, and PLL GND (analog)
20
C
OUT
O
Outputs chrominance signal. External simple LPF for clock elimination recommended.
21
NC
−
Non connection
22
DAVRB
−
DAC output range D lower limit voltage.
Stabilize by attaching a 0.01
µ
F capacitor.
23
DAVRT
−
DAC output range D upper limit voltage.
Stabilize by attaching a 0.01
µ
F capacitor.
24
Y
OUT
O
Outputs luminance signal. External simple LPF for clock elimination recommended.
