•
Shutter: electronic rolling shutter
•
Maximum exposure interval: 1968 x t
row
(where t
row
= the minimum sampling period
of the rolling shutter limited by the time-multiplexed ADC circuit)
•
Proprietary OmniBSI
™
(
B
ack
S
ide
I
llumination) pixel architecture provides
significant performance benefits over front-side illumination such as increased light
sensitivity per unit area, improved quantum efficiency, reduced crosstalk and
reduced photo-response non-uniformity.
•
System-On-a-Chip (SOC) processing:
◦
Field integration synchronous pixel readout with line-by-line transfer of the pixel
data to an analogue amplifier to form a balanced signal ready for analogue-to-
digital conversion (ADC).
◦
10 bit ADC provides 8 to 10 bit raw RGB data. The ADC can operate at up to
27 MHz and is fully synchronised to the pixel clock (see PLL below). The actual
ADC conversion rate is determined by the frame rate.
◦
Automatic exposure, white balance, band filter and black level control with
manual overrides provided by firmware interface.
◦
Programmable 16 zone size/position/weight control, cropping windowing and
panning.
◦
Lens correction (‘LENC’ i.e. a programmable fixed pattern of gain that varies
across the sensor area to compensate for uneven illumination caused by the
lens optics)
◦
System clock control is via an on-chip phase locked loop (PLL) that generates
a default 96 MHz clock from a 6-27 MHz input clock. An inside programmable
clock divider is used to generate different frame rate timing. The full 5
megapixel frame is read at a rate 15 FPS with a pixel clock of 80 MHz. Lower
resolutions are produced by cropping, subsampling or binning the full frames
and are read at the following rates and pixel clocks: 1080p at 30 FPS / 68 MHz,
960p at 45 FPS / 91.2 MHz, 720p at 60 FPS / 92 MHz, VGA at 90 FPS / 46.5
MHz and QVGA at 120 FPS / 32.5 MHz.
Note that these FPS are the rates
at which the CMOS SOC reads the frames and are NOT the maximum
frame rates available from the AF51 camera
(those actual frame rates are
dependent on the AF51 firmware and limitations of the USB 2.0 connection –
see later for those frame rates).
◦
Embedded 1.5 V regulator for core power
OptArc AF51 Camera Page 22 of 99 User Guide v1.02
