MNL-1024 Rev A
23
and directly via USB are active and unmasked. This also means that electronic dark correction is not available on the Flame-NIR+. An
invalid pixel is defined as a pixel that
has an abnormally high amount of dark current (a “hot” pixel) or
which has an abnormally low
responsivity (a “dead” pixel)”.
CCD Detector Reset Operation
At the start of each integration period, the detector transfers the signal from each pixel to the readout registers and resets the pixels.
The total amount of time required to perform this operation is ~8-9
s. The user needs to account for this time delay when the pixels
are optically inactive, especially in the external triggering modes.
Strobe Signals
Single Strobe
The Single Strobe signal is a programmable TTL pulse that occurs at a user-determined time during each integration period. This
pulse has a user-defined High Transition Delay and Low Transition Delay. The pulse width of the Single Strobe is the difference
between these delays. It is only active if the Lamp Enable command is active.
Synchronization of external devices to the spectrometer's integration period is accomplished with this pulse. The Strobe Delay is
specified by the Single Strobe High Transition Delay (SSHTD) and the Pulse Width is specified by the Single Strobe Low Transition
Delay (SSLTD) minus the Single Strobe High Transition Delay (PW = SSLTD
–
SSHTD). Both values are programmable in 500 ns
increments for the range of 0 to 65,535 (32.7675 ms).
The timing of the Single Strobe is based on the Start of Integration (SOI). SOI occurs on the rising edge of
ROG, which is used to
reset the detector. In all trigger modes using an External Trigger, there is a fixed relationship between the trigger and the SOI. In the
Normal mode and Software Trigger mode, the SOI still marks the beginning of the Single Strobe, but due to the nondeterministic
timing of the software and computer operating system, this timing will change over time and is not periodic. That is, at a constant
integration time, the Single Strobe will not be periodic, but it will indicate the start of the integration.
The Trigger Delay (TD) is another user programmable delay, which specifies the time in 500 ns increments that the SOI will be
delayed beyond the normal Start of Integration Delay (SOID).
An example calculation of the Single Strobe timing follows:
If the TD = 1 ms, SSHTD = 50 ms, and SSLTD = 70 ms, then the rising edge of the Single Strobe will occur approximately 51.82 ms (1
ms + 50 ms + 8.2 us) after the External Trigger Input goes high and the Pulse Width will be 20 ms (70 ms
–
50 ms).
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