NXP Semiconductors
UM11379
UJA116xA evaluation boards
2.2.4 VIO/V1 connections (UJA1166A-EVB)
A V
IO
supply is needed for the digital IOs. The V
IO
voltage must be aligned with the MCU
interface supply voltage. V
IO
is not needed in Sleep mode.
The V1 supply voltage is generated by the internal 5 V regulator and is intended to
supply peripheral circuitry, e.g. additional CAN transceivers. Detailed information on
the functionality and operation of the UJA1166A can be found in the data sheet and
application hints (see
).
UJA1166A
UJA1166A-EVB
VIO (pin 5)
J3-09 or J5-05: connect MCU-compatible supply voltage
V1 (pin 3)
J3-08: connect peripherals to be supplied from V1
Table 6. VIO/V1 connections
The V
IO
supply can be connected to either J3 or J5. The V1 output voltage is available
on J3. J3 is located on the top of the evaluation board and J5 is mounted on the bottom.
Decoupling capacitor C8 is provided to stabilize output voltage on V1 and remove noise.
Red LED D4 lights up once the V1 output is present.
VIO(p5)
V1(p3)
GND(p2)
C8
4.7 µF
J3
J5
aaa-040308
UJA1166A
C3
10 nF
R10
0 Ω
R9
1 kΩ
D4
LED
VIO
VIO
GND
V1
GND
Figure 5. V1 and VIO supply connection options (only relevant for UJA1166A-EVB)
UM11379
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User manual
Rev. 1 — 23 April 2021
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