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NXP Semiconductors
UM11379
UJA116xA evaluation boards
R1
1 k
R6
10 k
R7
10 k
R9
1 k
D4
D2
LED_GRN
SILK=BAT
PB_WAKE
SW1
SW_SPST_TH
LED_RED
SILK=V1
HDR_1X2
CON PWR 3
12 V
BAT
BAT
V1_LED
B
AT
_L
E
D
A
2 4
1 3
C
R5
10 k
C
A
A
C
CTS_SDO
RXD
TXD
SILK=GND
SILK=12 V
2
1
J2
HDR_1X2
SILK=CAN
PORT_CANH
PORT_CANL
SILK=H
SILK=L
2
1
J1
3
1
2
S
H
1
S
H
2
J6
BAT 10
2 15
U1
TXD 1
V1 3
RXD
CANH
UJA1168ATK/F
CANL
4
13
12
VIO_RSTN
SDO
GND
EPAD
6
NC_INH_VEXT
INH 7
D1
PMEG3020EH
C1
100 µF
C2
0.1 µF
C7
0.01 µF
TP12
TP13
R3
62
R2
62
L1
100 uH
C6
51 pF
R8
10 kΩ
C5
51 pF
C4
4700 pF
C3
0.01 µF(1)
C8
4.7 µF
J3
J4
J5
aaa-040338
R4, 0 (1)
R11, 0
R10, 0 (1)
12
HDR_1X12
USER INTERFACE
ARDUINO INTERFACE
HDR_2X10
SILK=GND
11
10
9
NC_WAKE
NC_INH_VEXT
VIO_RSTN
STBN_SLPN_SCSN
STBN_SLPN_SCSN
NC_SDI
CTS_SDO
TXD
RXD
NC_SCK
BUF_VCC_V1
NC_SCK
NC_SDI
CTS_SDO
RXD
TXD
SILK=RST
8
SILK=V1
SILK=WAKE
SILK=INH
7
SILK=GND
6
SILK=SCS
5
SILK=TXD
SILK=RXD
SILK=SCS
SILK=SDO
SILK=SDI
SILK=SCK
SILK=GND
4
3
SILK=SDO
2
SILK=RXD
SILK=SCK
SILK=SDI
1
SILK=TXD
HDR_1X2
JUMPER (DEFAULT) = ON
2
1
J8
2
1
J7
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
2
4
6
8
10
12
14
16
HDR_2X8
1
3
5
7
9
VCC
RSTN
V1_VIO
SILK=VIO
SILK=GND
VIO_RSTN
SILK=RST
SILK=VIN
SILK=VIN
11
13
15
12 V
BUF_VCC_V1
HDR 1X2
JUMPER (DEFAULT) = ON
VIN
BAT
TP14
TP8
TP15
TP6
TP5
TP11
TP4
TP3
TP10
TP7
TP9
TP1
TP2
RSTN
5
WAKE
9
SCSN
NC_WAKE
STBN_SLPN_SCSN
14
SDI
NC_SDI
11
SCK
NC_SCK
8
CANH
CANL
2
3
D3
PESD1CAN
1
1
2
CAN_T
3
4
(1) Component not populated.
Figure 14. UJA1168AF-EVB schematic diagram
aaa-040337
R1
1 k
R6
10 k
R7
10 k
R5
10 k (1)
R4, 0 (1)
(1)
R11, 0 (1)
R10
R9
1 k
D4
D2
LED_GRN
SILK=BAT
LED RED
SILK = V1
12
HDR_1X12
USER INTERFACE
ARDUINO INTERFACE
HDR_1X2
CON PWR 3
12 V
BAT
V1_LED
B
AT
_L
ED
A
C
C
A
A
C
HDR_2X10
SILK=GND
11
10
9
NC_WAKE
NC_INH_VEXT
VIO_RSTN
STBN_SLPN_SCSN
STBN_SLPN_SCSN
NC_SDI
CTS_SDO
TXD
RXD
NC_SCK
BUF_VCC_V1
NC_SCK
NC_SDI
CTS_SDO
RXD
TXD
SILK=VIO
8
SILK=V1
7
SILK=GND
SILK=WAKE
SILK=INH
6
SILK=SLP
5
SILK=TXD
SILK=RXD
SILK=SLP
SILK=CTS
SILK=GND
4
3
SILK=CTS
2
SILK=RXD
1
J3
SILK=TXD
SILK=GND
SILK=12 V
2
1
J2
HDR_1X2
JUMPER (DEFAULT) = ON
2
1
J8
2
1
J7(1)
HDR_1X2
SILK=CAN
PORT_CANH
PORT_CANL
SILK=H
SILK=L
2
1
J1
3
1
2
S
H
1
S
H
2
J6
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
2
4
6
8
10
12
14
16
J4
HDR_2X8
1
3
5
7
9
VCC
RSTN
V1_VIO
SILK=VIO/V1
SILK=GND
VIO_RSTN
SILK=VIN
SILK=VIN
11
13
15
J5
1
15
U1
UJA1166ATK
TXD
TXD
RXD
GND 2
V1 3
VIO_RSTN
CTS_SDO
NC_INH_VEXT
EP
D1
PMEG3020EH
C1
100 µF
C2
0.1 µF
TP12
TP13
TP6
R3
62
R2
62
R8
10 k
L1
100 uH
C6
51 pF
C5
51 pF
C4
4700 pF
BUF_VCC_V1
12 V
BUF_VCC_V1
HDR 1X2
DNP
VIN
BAT
BAT
TP5
TP14
TP4
TP3
TP11
TP15
TP10
C8
4.7 µF
C3
0.01 µF
TP1
TP2
2
3
D3
PESD1CAN
1
1
2
CAN_T
3
4
RXD 4
VIO 5
CTS 6
INH
7
14 SLP
CANH
13
CANL
12
IC_2
11
BAT
10
WAKE
9
IC_1
STBN_SLPN_SCSN
CANH
CANL
NC_SDI
NC_WAKE
NC_SCK
8
PB_WAKE
SW1
SW_SPST_TH
2 4
1 3
C7
0.01 µF
TP9
TP8
TP7
(1) Component not populated.
Figure 15. UJA1166A-EVB schematic diagram
UM11379
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© NXP B.V. 2021. All rights reserved.
User manual
Rev. 1 — 23 April 2021
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