NXP Semiconductors
UM11697
RDGD31603PSMKEVM three-phase inverter kit
Note:
Phase U can be configured for performing double-pulse and short-circuit testing.
To enable short-circuit testing, two resistors (R43, R56) must be pulled from PWMALT
phase U signals to disable Deadtime control on Phase U Gate drivers.
Figure 32. Pulse tab
5.4 Troubleshooting
Some common issues and troubleshooting procedures are detailed below. This is not an
exhaustive list by any means, and additional debugging may be needed:
Problem
Evaluation
Explanation
Corrective action(s)
Check PWM jumper position
on translator board.
Incorrect PWM jumpers
obstruct signal path but do
not report fault.
Set PWMH_SEL (J4) and
PWML_SEL (J5) jumpers
properly,for desired control
method:
•
3.3 V to 5.0 V translator
board reviewed in
Section4.4
.
Check PWM control signal.
Ensure that proper PWM
signal is reaching GD3160.
Monitor EXT_PWML (TP14)
and EXT_PWMH (TP15) for
commanded PWM state.
Check FSENB status (see
GD3160 pin 15, STATUS3).
PWM is disabled when
FSENB = LOW.
Set pin FSENB = HIGH (pin
15) to continue
No PWM output (no fault
reported).
Check CONFIG_EN bit
(MODE2).
PWM is disabled when
CONFIG_EN is logic 1.
Write CONFIG_EN = logic 0
to continue
No PWM output (fault
reported).
Check VGE fault (VGE_FLT). A short on IGBT or SiC
module gate, or too low
of VGEMON delay setting
causes VGE fault, locking out
PWM control of the gate.
Clear VGE_FLT bit
(STATUS2) to continue.
Increase VGEMON delay
setting (CONFIG6).
If safe operating condition
can be guaranteed, set
VGE_FLTM (MSK2) bit to
logic 0, to mask fault.
Table 7. Troubleshooting
UM11697
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User manual
Rev. 1 — 10 December 2021
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