NXP Semiconductors
UM11603
RDGD31603PHSEVM three-phase inverter reference design
Name
Description
J2
Jumper 1-2 default - DC supply for VSUP to gate drivers supplied
through J1 terminal connection
Jumper Open VSUP supply to gate drivers isolated
J13
Jumper 1-2 default MOSI – Normal mode three device daisy chain 3
device high-side, 3 device low-side (x3 – 2 channel)
Jumper 2-3 MOSI - Six device daisy chain all six gate drivers daisy
chained together (x6 – 1 channel)
J14
Jumper 1-2 default MISO-Normal mode three device daisy chain 3
device high-side, 3 device low-side (x3 – 2 channel)
Jumper 2-3 MISO - Six device daisy chain all six gate drivers daisy
chained together (x6 – 1 channel)
J50
Jumper open default CSB-Normal mode three device high-side, 3 device
low-side (x3 - 2 channel)
Jumper 1-2 CSB - Six device daisy chain all six gate drivers daisy
chained together (x6 - 1 channel)
Phase current feedback connector Current feedback connections from U, V, and W phases
Resolver signals connector
Resolver excitation signals (see schematic for more information)
MCU Signals
Two-row header of all MCU signals for debug and development. (See
schematic for details)
PCIe/MCU connector
2x32 PCIe connector for easy connection to MPC5777CDEVB or
MPC5744P via PCIe cable (S32SDEV-CON18)
J1 VPWR terminal connector
Used for external low voltage power supply connection typically 12 V
Vbatt
Table 4. RDGD31603PHSEVM connector and jumper descriptions
4.2.6 Power supply test points
Figure 6. Power supply test point locations
UM11063
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
User manual
Rev. 1 — 18 August 2021
12 / 40
