Modes of Operation
MSC8113 Reference Manual, Rev. 0
Freescale Semiconductor
25-9
25.4.4.2 Echo Mode
The Ethernet controller allows the MII to operate in Echo mode using the following
configuration:
Select MII mode (MIIGSK_CFGR[IFMODE] = 00)
Clear MACCFG1R[MIILB]
Clear MIIGSK_CFGR[LBMODE]
Set MIIGSK_CFGR[EMODE]
Selecting this mode causes the Ethernet controller MII to receive inputs from the MII PHY that
are looped back to the Ethernet controller MII transmit outputs of the MII PHY. In this mode, the
MII PHY receives the frame.
25.4.4.3 Low-Power Stop Mode
The Ethernet controller enters Low-Power Stop mode when the following conditions are met; the
Ethernet controller responds with a stop acknowledgement:
Set SCR1[ETH_STC].
Clear all the IMASK register Interrupt Events Enable bits.
No Ethernet controller access is pending on the Internal Peripheral Interface (IPI) line.
In Low Power Stop mode, the Ethernet controller conversion operation is still enabled, but the
Ethernet controller registers cannot be accessed, and no new interrupts are captured because the
Ethernet controller output interrupt line is deasserted. To exit from Low Power Stop mode, clear
SCR1[ETH_STC] in the IP master block. To clear all pending interrupts when in MII or RMII
mode, write a value of 0xFFFFFFF to the IEVENT register. You can reenable the interrupt
sources in the IMASK register as required. To clear all pending interrupts when in SMII mode,
write a value of 0xFFFFFFFF to the MIIGSK_IEVENT and the IEVENT registers. You can
reenable the interrupt sources in MIIGSK_IMASK and IMASK registers as required.
Note:
The MIIGSK_IMASK and MIIGSK_IEVENT registers are valid only in SMII mode.
25.4.5 Management Interface
The management interface (ETHMDIO/ETHMDC) is identical to that defined in IEEE Std.
802.3u™ for all normal operating modes (MII/RMII/SMII).
Содержание MSC8113
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