AN4536 Application Note Rev. 2.0 1/2014
28
Freescale Semiconductor
Hardware Considerations
3
Hardware Considerations
The minimum system requirements to allow programming of the OTP fuses are:
1.
An I
2
C communication bridge to communicate with the PF0100
2.
A 1.7 V to 3.6 V power supply at VDDIO (power to I
2
C block and pull-up resistors for the SCL and SDA
lines). Using the KITPFPGMEVME requires a minimum of 3.0 V at VDDIO
3.
An 9.5 V/9.25 V, 100 mA power supply at VDDOTP bypassed by 2 x 10
μ
F capacitors. The voltage
depends on the silicon revision used. See section
OTP Programming Example
for details.
4.
An input voltage of 3.3 V at the VIN pin
Figure 1
shows the minimum requirements for programming the MMPF0100. For programming the MMPF0100 on
an application board some hardware considerations have to be made.
.
Figure 1. Minimum OTP Programming Requirements Diagram
VPGM
SDA
SCL
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INTB
PMPF0100
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
SW1CLX
SW1CIN
SW1CFB
SW1VSSSNS
LICELL
VGEN6
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
G
N
DRE
F1
VGEN
1
VIN1
VGEN
2
SW4
F
B
SW4
IN
SW4
L
X
SW2
L
X
SW2
IN
SW2
IN
SW2
F
B
VGEN
3
VIN2
VGEN
4
PWR
O
N
VDD
IO
SC
L
SD
A
VCO
R
ER
EF
VCORED
IG
VIN
VC
O
R
E
GN
DR
E
F
VD
DO
T
P
SW
BS
T
L
X
SWB
S
T
IN
SWB
S
T
F
B
VSNVS
C
PGM
C
1
C
2
C
3
C
4
PROGRAMMING
INTERFACE
C
1
= 0.22 uF, 20 V, ceramic
C
2
= 1.0 uF, 20 V, ceramic
C
3
= 0.1 uF, 20 V, ceramic
C
4
= 1.0 uF, 20 V, ceramic
Optional:
3.0 V Lithium-Ion Coin Cell
Allows “Try-Before-Buy”
For Development
R
2
R
1
4.7 K
4.7 K
C
5
C
PGM
= 2 x 10 uF + 1 x 0.1 uF,
20 V, ceramic
C
5
= 0.1 uF, 20 V, ceramic
V3.3
GND
NC
NC
PWRON
R
3
100 K
1
2
3
4
5
6
7
8
R
4
10 K
VSNVS
VSN
VS