Slow-loop interrupt generation - TMR1
The QuadTimer module TMR1 is used to generate the slow-loop interrupt.
• The slow loop is usually ten times slower than the fast loop. Therefore, the interrupt is generated after the counter counts
from CNTR0 = 0 to COMP1 = IPG CLK ROOT / (16U * Speed Loop Freq). The speed loop frequency is set in the
M1_SPEED_LOOP_FREQ macro and equals 1000 Hz.
• An interrupt (which serves the slow-loop period) is enabled and generated at the reload event.
FreeMASTER communication—LPUART1
LPUART1 (Low-Power Universal Asynchronous Receiver and Transmitter) is used for the FreeMASTER communication
between the MCU board and the PC.
• The baud rate is set to 115200 bit/s.
• The receiver and transmitter are both enabled.
• The other settings are set to default.
3.2 RT family - CPU load and memory usage
The following information apply to the application built using the MCUXpresso IDE in the debug and release configurations. The
tables below show the memory usage and CPU load. The memory usage is calculated from the
.map
linker file, including the 4-KB
FreeMASTER recorder buffer allocated in RAM. The CPU load is measured using the SysTick timer. The CPU load is dependent
on the fast-loop (FOC calculation) and slow-loop (speed loop) frequencies. In this case, it applies to the fast-loop frequency of 10
KHz and the slow-loop frequency of 1 KHz. The total CPU load is calculated using the following equations:
Where:
CPU
fast
- the CPU load taken by the fast loop.
cycles
fast
- the number of cycles consumed by the fast loop.
f
fast
- the frequency of the fast-loop calculation (10 KHz).
f
CPU
- CPU frequency.
CPU
slow
- the CPU load taken by the slow loop.
cycles
slow
- the number of cycles consumed by the slow loop.
f
slow
- the frequency of the slow-loop calculation (1 KHz).
CPU
total
- the total CPU load consumed by the motor control.
Table 5. i.MX RT1170 CPU load and memory usage (similar for RT1160)
debug configuration
release configuration
Board FLASH
113 152 B
Usage 0.67%
68 704 B
Usage 0.41%
Board SRAM
17 428 B
Usage 0.03%
17 404
Usage 0.03%
Table continues on the next page...
NXP Semiconductors
RT crossover processors features and peripheral settings
MCUXpresso SDK Field-Oriented Control (FOC) of 3-Phase PMSM and BLDC motors, Rev. 0, 01/2022
User Guide
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