NXP Semiconductors MC9S08QL4, Справочное руководство

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 215
15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
4
MSnA
Mode select A for TPM channel n. When CPWMS and MSnB are cleared, the MSnA bit configures TPM channel
n for input capture mode or output compare mode. Refer to
Table 15-9 for a summary of channel mode and setup
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger.
3–2
ELSnB
ELSnA
Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
and shown in
Table 15-9 , these bits select the polarity of the input edge that triggers an input capture event, select
the level that is driven in response to an output compare match, or select the polarity of the PWM output.
If ELSnB and ELSnA bits are cleared, the channel pin is not controlled by TPM. This configuration can be used
by software compare only, because it does not require the use of a pin for the channel.
Table 15-9. Mode, Edge, and Level Selection
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X XX 00 Pin is not controlled by TPM. It is reverted to general purpose I/O or
other peripheral control
0 00 01 Input capture Capture on rising edge only
10 Capture on falling edge only
11 Capture on rising or falling edge
01 00 Output compare Software compare only
01 Toggle output on channel match
10 Clear output on channel match
11 Set output on channel match
1X 10 Edge-aligned
PWM
High-true pulses (clear output on channel match)
X1 Low-true pulses (set output on channel match)
1 XX 10 Center-aligned
PWM
High-true pulses (clear output on channel match
when TPM counter is counting up)
X1 Low-true pulses (set output on channel match when
TPM counter is counting up)
7 6 5 4 3 2 1 0
R
TPMxCnV[15:8]
W
Reset 0 0 0 0 0 0 0 0
Figure 15-12. TPM Channel Value Register High (TPMxCnVH)
Table 15-8. TPMxCnSC Field Descriptions (continued)
Field Description