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2.3 DDR interface
The LS1046ARDB has a DDR4 dual inline memory module (DIMM) socket that contains a high-speed, dual-rank, 8 GB, x72
DDR4 unbuffered DIMM (UDIMM), MTA18ASF1G72AZ-2G3B1. The DDR interface includes all necessary termination and I/O
power, and is routed such that maximum performance of the DDR memory bus can be achieved. The figure below shows the
DDR diagram of the LS1046ARDB.
LS1046A
M1_MA[0:13], M1_BA[0:1], M1_BG[0:1]
M1_MRAS_B, M1_MCAS_B, M1_MWE_B
M1_MCK[ 0:1]_P/N, MCKE[0:1,], MODT[0:1]
M1_MCS_B[0:3]
M1_MDQ[0:63]
M1_MDQS_P,N[0:8], M1_MDM[0:8]
M1_MALERT_B, M1_MPAR
M1_MECC[0:7]
DDR4 DIMM socket
288-pin
Figure 7. DDR diagram
Following are characteristics of the LS1046ARDB DDR interface:
• Supports data rates of up to 2100 MT/s
• Supports 64-bit data bus
• Supports an onboard dual-rank, 8 GB, x72 unbuffered DDR4 memory module (eight data byte lanes + ECC) on a DDR4
DIMM socket
• Supports double-bit error detection and single-bit error correction ECC (8-bit check word across 64-bit data)
• Supports four chip selects
The LS1046ARDB DDR interface can work with any JEDEC-compliant, 288-pin, DDR4 UDIMM or RDIMM module.
The DIMM used in the board is only a representative DIMM (MTA18ASF1G72AZ-2G3B1).
NOTE
DDR interface
QorIQ LS1046A Reference Design Board Reference Manual, Rev. 2, 30 May 2019
NXP Semiconductors
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