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2.2 Clocks

The figure below shows the clock diagram of the LS1046ARDB. Most of the clocks in the board are produced by the IDT
6V49205BNLGI clock generator.

LS1046A

Clock generator

(IDT 6V49205BNLGI)

CPLD

10G PHY

AQR107

DIFF_SYSCLK_[P,N]
SYSCLK_18

SD1_REFCLK1_[P,N]

CLK SEL

SD1_REFCLK2_[P,N]

Osc.

156.25 MHz

831724KILFT

PCIe slot 1

(mini-PCIe)

PCIe slot 2

MPCIE_CLK_[P,N]

100 MHz

RTCCLK_18

32.768 kHz (LVCMOS)

RGMII2

RGMII1

XFI retimer

PCIe slot 3

PCIE2_CLK_[P,N]

SD2_REFCLK1_[P,N]

SGMII1

CLKSEL /

buffer

831724KILFT

XGT1588_CLK_[P,N]

100 MHz (LP-HCSL)

100 MHz (LP-HCSL)

25 MHz

25 MHz

100 MHz

100 MHz (HCSL)

100 MHz (LP-HCSL)

100 MHz (LP-HCSL)
100 MHz (LVCMOS)

100 MHz (LP-HCSL)

DDRCLK_18

100 MHz (LVCMOS)

(LVDS)

100/156.25 MHz

(HCSL)

(U31)

(Y3)

(U34)

SD2_REFCLK2_[P,N]

100 MHz (LP-HCSL)

Y2

(HCSL)

PCIE1_CLK_[P,N]
100 MHz (HCSL)

(HCSL)

CLK_50M_[P,N]

50 MHz

Crystal

(Y1)

XFI1_REFCLK

25 MHz

 

(LVCMOS)

Osc.

(Y500)

(U30)

PLD_CLK

32.768 kHz

 

(LVCMOS)

Osc.

(Y4)

SGMII2

(LVCMOS)

25MHZ_EC1_RGMII

25MHZ_CPLD

25 MHz

(LVCMOS)

25MHZ_EC2_RGMII

25 MHz

(LVCMOS)

25MHZ_EC3_SGMII

25 MHz

(LVCMOS)

25MHZ_EC4_SGMII

25

 MHz

 (LVCMOS)

Figure 6. LS1046ARDB clock diagram

The table below provides details of different clocks of the LS1046ARDB.

Table 6. LS1046ARDB clocks

Clock generator

Clocks

Specifications

Destination

Y2: Crystal

25MHz_IN1

• Frequency: 25 MHz

U34 clock generator

U34: 6V49205BNLGI

PCIE_REFCLK_S_[P, N]

• Frequency: 100 MHz

• Output type: LP-HCSL

• Operating voltage: 3.3 V

U30 PCIe clock buffer

DIFF_SYSCLK_[P, N]

• Frequency: 100 MHz

• Output type: LP-HCSL

• Operating voltage: 3.3 V

LS1046A processor (primary system
clock)

SYSCLK_18

• Frequency: 100 MHz

• Output type: LVCMOS

• Operating voltage: 1.8 V

LS1046A processor (secondary
system clock)

Table continues on the next page...

LS1046ARDB Functional Description

QorIQ LS1046A Reference Design Board Reference Manual, Rev. 2, 30 May 2019

20

NXP Semiconductors

Содержание LS1046ARDB

Страница 1: ...QorIQ LS1046A Reference Design Board Reference Manual Supports LS1046ARDB Revision B NXP Semiconductors Document Number LS1046ARDBRM Reference Manual Rev 2 30 May 2019...

Страница 2: ...urement 36 2 16 DIP switches 37 2 17 LEDs 39 2 18 Processor configuration 41 Chapter 3 Programming Model 42 3 1 CPLD Major Revision Register CPLD_VER 43 3 2 CPLD Minor Revision Register CPLD_VER_SUB 4...

Страница 3: ...Register Take Effect Enable Register REG_VDD_EN 58 3 18 VDD Voltage Control Register REG_VDD_SEL 59 3 19 SFP Module Tx Enable Register REG_SFP_TXEN 60 3 20 SFP Module Status Register REG_SFP_STATUS 6...

Страница 4: ...3 Figure 8 SerDes architecture 25 Figure 9 Ethernet RGMII 27 Figure 10 IEEE 1588 interface overview 28 Figure 11 EMI routing 29 Figure 12 USB architecture 30 Figure 13 IFC block diagram 31 Figure 14 S...

Страница 5: ...upported on SerDes protocols 26 Table 10 Wi Fi module configuration 27 Table 11 Ethernet port locations 27 Table 12 SD card pinout configuration 32 Table 13 UART Selection 33 Table 14 LS1046ARDB RS 23...

Страница 6: ...iations used in this document Table 1 Acronyms and abbreviations Acronym abbreviation Description CPLD Complex programmable logic device CTS Clear to send DDR Double data rate DIP Dual inline package...

Страница 7: ...erface SLC Single level cell SPD Serial presence detect SPI Serial peripheral interface TAP Test access port TSEC Three speed Ethernet controller UART Universal asynchronous receiver transmitter UDIMM...

Страница 8: ...LS1046A Design Checklist AN5252 This document provides recommendations for new designs based on the LS1046A This document can also be used to debug newly designed systems by highlighting those aspect...

Страница 9: ...S1046ARDB features Board feature Processor feature used Description Processor QorIQ LS1046A processor For details on the LS1046A processor see QorIQ LS1046A Reference Manual NOTE Table continues on th...

Страница 10: ...ne 0 Supports a mini PCIe x1 Gen 1 2 3 slot for a Wi Fi module Lane 1 Supports a PCIe x1 Gen 1 2 3 slot for a PCIe x1 card Lane 2 Supports a PCIe x1 Gen 1 2 3 slot for a PCIe x1 card Lane 3 Supports a...

Страница 11: ...hrough a 1x2 multiplexer Operates at EVDD 1 8 V for SDHC card 3 3 V for eMMC memory UART Two DUART modules DUART1 and DUART2 each containing two UARTs UART1 and UART2 are connected to a 1x2 RJ45 conne...

Страница 12: ...DVDD 3 3 1 8 V for EVDD 3 3 V for USB HVDD 1 8 V for OVDD and LVDD 1 0 9 V for SVDD 1 35 V for XVDD 2 5 V for TVDD 1 8 V GND for TA_PROG_SFP and PROG_MTR 0 85 V for AQR107 core 2 1 V for AQR107 VA 3 3...

Страница 13: ...rovides option for 25 MHz clock output CLKOUT from clock generator to Ethernet RGMII and SGMII transceivers Supports 100 MHz XGT1588_CLK and 50 MHz to 10G PHY AQR106 107 CPLD Supports 32 768 kHz for P...

Страница 14: ...Supports micro USB port to access serial port as console for debug 1 5 Board top bottom views The figure below shows the LS1046ARDB top view Figure 2 LS1046ARDB top view The figure below shows the LS...

Страница 15: ...Figure 3 LS1046ARDB bottom view Board top bottom views QorIQ LS1046A Reference Design Board Reference Manual Rev 2 30 May 2019 NXP Semiconductors 15...

Страница 16: ...32 I2C interface on page 33 JTAG interface on page 35 CMSIS DAP interface on page 36 Temperature measurement on page 36 DIP switches on page 37 LEDs on page 39 Processor configuration on page 41 2 1...

Страница 17: ...tes the power up sequencing 1 is the first power up rail NXP DC DC LTC DC DC LTC LDO SoC Peripherals Legends Figure 4 LS1046ARDB power supply block diagram 2 1 1 Primary power supply The LS1046ARDB ca...

Страница 18: ...SD card slot mini PCIe and PCIe slots and muxes Supply for MC34VR500V8ES MC34716EP LT3085 and LT3065 U13 power supply devices U523 LT8640 Linear Technology 5_0V 5 V at 2 A Supply for SATA connector an...

Страница 19: ...nnected to an AC power outlet through a 12 V DC power adapter and the power switch on the board is turned ON the board gets 12 V input power With the 12 V power available the remaining power supplies...

Страница 20: ...0M_ P N 50 MHz Crystal Y1 XFI1_REFCLK 25 MHz LVCMOS Osc Y500 U30 PLD_CLK 32 768 kHz LVCMOS Osc Y4 SGMII2 LVCMOS 25MHZ_EC1_RGMII 25MHZ_CPLD 25 MHz LVCMOS 25MHZ_EC2_RGMII 25 MHz LVCMOS 25MHZ_EC3_SGMII 2...

Страница 21: ...ncy 100 MHz Output type LP HCSL Operating voltage 3 3 V LS1046A processor SerDes2 PLL 2 clock 25MHZ_EC1_RGMII Frequency 25 MHz Output type LVCMOS Operating voltage 3 3 V RGMII PHY U17 reference clock...

Страница 22: ...z Output type HCSL Operating voltage 3 3 V 10G AQR107 PHY 1588 clock Y1 Crystal CLK_50M_ P N Frequency 50 MHz 10G AQR107 PHY reference clock Y3 Oscillator 156P25M_CLK_ P N Frequency 156 25 MHz Output...

Страница 23: ...ALERT_B M1_MPAR M1_MECC 0 7 DDR4 DIMM socket 288 pin Figure 7 DDR diagram Following are characteristics of the LS1046ARDB DDR interface Supports data rates of up to 2100 MT s Supports 64 bit data bus...

Страница 24: ...ed SerDes combinations The LS1046A SerDes block supports the following features Supports PCIe 5 0 Gbit s with x1 operation SATA 3 0 6 0 Gbit s SGMII 1G 1 25 Gbit s and SGMII 2 5G 3 125 Gbit s Three PC...

Страница 25: ...llowing table lists the supported SerDes embedded devices Table 7 LS1046ARDB SerDes embedded devices Manufacturer Part number Description 3M 5622 2222 ML SATA 3 0 data header WIN WIN PRECISION WPES 03...

Страница 26: ...e provides the lanes and speeds supported on the SerDes protocols Table 9 Lanes and speeds supported on SerDes protocols Mode Number of lanes supported Speed SGMII 1G x1 1 25 Gbit s PCIe Gen1 2 3 x1 2...

Страница 27: ...shown in the following figure LS1046A RTL8211FS RTL8211FS dTSEC4 dTSEC3 MDIO MDC EMI1_MDC MDIO address 2 address 1 P2 1588 header Figure 9 Ethernet RGMII The table below lists the Ethernet port locat...

Страница 28: ...588 PTP is supported at a basic level with internal logic and the use of a precision 125 00 MHz reference clock with an accuracy of 25 ppm The figure below shows an overview of the IEEE 1588 block QIX...

Страница 29: ...low direct connection to the USB ports with appropriate protection circuitry and power supplies USB1 and USB2 ports are powered by a NX5P2190UK device which supplies 5 V power at up to 1 2 A The power...

Страница 30: ...ata bus USB2_VBUS USB1_VBUS USB3_VBUS J 2 CPLD J 1 Figure 12 USB architecture 2 8 IFC interface The LS1046ARDB integrated flash controller IFC has the following features Supports 1 8 V I O voltage Imp...

Страница 31: ...Spansion S25FS512SDSMFI011 quad SPI serial flash memories U45 and U48 and an external QSPI emulator J23 with 20 pin 0 05 pitch header SamTec TFM 110 02 S D SN K TR or equivalent The LS1046ARDB suppor...

Страница 32: ...er Signal name Description Pin 1 DATA2 Data signal 1 Pin 2 DATA3 Data signal 2 Pin 3 CMD I O Input output command Pin 4 GND Supply voltage negative Pin 5 VDD Supply voltage positive Pin 6 CLK Clock si...

Страница 33: ...n SW4 4 switch setting Selection ON CMSIS DAP OFF RJ45 The table below describes the LS1046ARDB RS 232 interface UART ports Table 14 LS1046ARDB RS 232 interface UART ports UART port Destination Power...

Страница 34: ...p I2C bus I2C address Device Manufacturer Description I2C1 0x52 0x53 CAT24C05 ON Semiconductor Half of the device is used as generic EEPROM The other half is used to store system ID and MAC address 0x...

Страница 35: ...s defined by the plugged in PCIe card Standard PCIe x1 slot 0x51 PCF2129AT Pericom Semiconductor Real time clock RTC 2 13 JTAG interface The ARM JTAG architecture is shown in the figure below LS1046A...

Страница 36: ...serial channel CMSIS DAP features a mass storage device MSD boot loader which provides a quick and easy mechanism for loading different CMSIS DAP applications such as flash programmers run control deb...

Страница 37: ...e sensor Part identifier Part number I2C bus I2C address Operating voltage U35 ADT7461 I2C1 0x4C 3 3 V 2 16 DIP switches The LS1046ARDB has three 8 pin dual inline package DIP switches SW3 SW4 and SW5...

Страница 38: ...S1046A processor default setting 1 JTAG header for CPLD programming SW_RST_MODE 8 7 6 5 4 3 2 1 CMSISDAP_EN SW_EVDD_SEL SD1REFCLK_SEL UART_SEL SW_BAKUP VDD_VOLT_SEL SW_RCW_SRC8 ON 1 SW4 2 VDD voltage...

Страница 39: ...program a bootable image on the eMMC flash When you boot from eMMC you cannot insert an SD card If you want to boot from an SD card insert a bootable SD card When an SD card is inserted eMMC will be...

Страница 40: ...reen SGMII1 link Yellow SGMII1 activity D10 Green yellow Chassis SGMII 2 Green SGMII2 link Yellow SGMII2 activity D11 Green yellow Chassis 10G COPPER Green AQR106 10G PHY link Yellow AQR106 10G PHY ac...

Страница 41: ...Not applicable Specifies RCW fetch location cfg_dram_type QSPI_B_SCK Not applicable Specifies DDR4 Affects GVDD power supply cfg_soc_use ASLEEP Specifies XVDD voltage supply 1 35 V cfg_gpinput 0 7 IFC...

Страница 42: ...G_RCW_SRC1 8 RW 00h 6h RCW Source Location POR Register 2 REG_CFG_RCW_SRC2 8 RW 00h 7h QSPI Flash Bank Setting Register REG_QSPI_BANK 8 RW 00h 8h System clock POR Register REG_SYSCLK_SEL 8 RW 00h 9h U...

Страница 43: ...ved W Reset 1000 0000 Fields Field Function 0 3 CPLD_VER CPLD_VER CPLD major revision number 4 7 Reserved 3 2 CPLD Minor Revision Register CPLD_VER_SUB Offset Register Offset CPLD_VER_SUB 1h Function...

Страница 44: ...n Register PCBA_VER Offset Register Offset PCBA_VER 2h Function Read this register to get PCBA revision Diagram Bits 0 1 2 3 4 5 6 7 R PCBA_VER Reserved W Reset 1000 0000 Fields Field Function 0 3 PCB...

Страница 45: ...eset and keep the value of CPLD register Diagram Bits 0 1 2 3 4 5 6 7 R SYSTEM_ Reserved W Reset 0 0000000 Fields Field Function 0 SYSTEM_RST SYSTEM_RST System hardware reset not reset value of CPLD r...

Страница 46: ...2 enable 0b POR REG_CFG_RCW_SRC Register 1 and 2 no effect default value 1b POR REG_CFG_RCW_SRC Register 1 and 2 take effect 1 POR_SYSCLK_ EN POR_SYSCLK_EN System clock POR register enable 0b POR REG_...

Страница 47: ...K_SEL Register no effect default value 1b REG_1588_CLK_SEL Register take effect 6 QSPI_BANK_E N QSPI_BANK_EN QSPI flash bank setting register enable 0b REG_QSPI_Bank Register no effect default value 1...

Страница 48: ...0010_0000_0 SDHC 0010_0010_0 QSPI default value 0100_1XXX_X Hard coded RCW Others Reserved 3 7 RCW Source Location POR Register 2 REG_CFG_RCW_ SRC2 Offset Register Offset REG_CFG_RCW_SRC2 6h Function...

Страница 49: ..._0 SDHC 0010_0010_0 QSPI default value 0100_1XXX_X Hard coded RCW Others Reserved 1 7 Reserved 3 8 QSPI Flash Bank Setting Register REG_QSPI_BANK Offset Register Offset REG_QSPI_BANK 7h Function Use t...

Страница 50: ...000 DEV 0 DEV 1 default value 001 DEV 1 DEV 0 010 EMU DEV 0 011 EMU DEV 1 100 DEV 0 EMU Others Reserved 3 7 Reserved 3 9 System clock POR Register REG_SYSCLK_SEL Offset Register Offset REG_SYSCLK_SEL...

Страница 51: ...rential clock default value 1 Single ended Clock 1 7 Reserved 3 10 UART1 Connection Control Register REG_UART1_SEL Offset Register Offset REG_UART1_SEL 9h Function Use this register to configure UART1...

Страница 52: ...to RJ45 1 UART1 to CMSIS DAP default value 1 7 Reserved 3 11 SerDes1 Reference Clock2 Setting Register REG_SD1R EFCLK_SEL Offset Register Offset REG_SD1REFCLK_SEL Ah Function Use this register to con...

Страница 53: ...Hz default value 1 7 Reserved 3 12 Ethernet Controller 2 Connection Control Register REG_ RGMII_1588_SEL Offset Register Offset REG_RGMII_1588_SEL Bh Function Use this register to configure ethernet c...

Страница 54: ...tion setting register 0 1588 Interface 1 RGMII PHY default value 1 7 Reserved 3 13 1588 Clock Source Control Register REG_1588_CLK_ SEL Offset Register Offset REG_1588_CLK_SEL Ch Function Use this reg...

Страница 55: ...ard clock generator default value 1 From 1588 Interface connector 1 7 Reserved 3 14 STATUS LED Control Register REG_STATUS_LED Offset Register Offset REG_STATUS_LED Dh Function Use this register to co...

Страница 56: ...fault value 1 LED On 1 7 Reserved 3 15 System Hardware Reset Register REG_GLOBAL_RST Offset Register Offset REG_GLOBAL_RST Eh Function Use this register to implement system hardware reset and initiali...

Страница 57: ...ssserted default value 1 Reset asserted 1 7 Reserved 3 16 SD or EMMC Interface Control Register REG_SD_EMM Offset Register Offset REG_SD_EMM Fh Function Use this register to select SD or eMMC interfac...

Страница 58: ...l 0 SD default value 1 eMMC 1 7 Reserved 3 17 VDD Voltage Control Register Take Effect Enable Register REG_VDD_EN Offset Register Offset REG_VDD_EN 10h Function Use this register to enable REG_VDD_SEL...

Страница 59: ...SEL register no effect default value 1 REG_VDD_SEL register take effect 1 7 Reserved 3 18 VDD Voltage Control Register REG_VDD_SEL Offset Register Offset REG_VDD_SEL 11h Function Use this register to...

Страница 60: ...ister before writing the VDD_SEL register VDD voltage control 0b VDD 1 0 V default value 1b VDD 0 9 V 1 7 Reserved 3 19 SFP Module Tx Enable Register REG_SFP_TXEN Offset Register Offset REG_SFP_TXEN 1...

Страница 61: ...trol 0b Tx enable default value 1b Tx disable 1 7 Reserved 3 20 SFP Module Status Register REG_SFP_STATUS Offset Register Offset REG_SFP_STATUS 13h Function Use this register to read the status of the...

Страница 62: ..._VALID SFP module Rx status 0b Normal operation default value 1b Receiver signal loss 2 XFI1_TX_FAUL T XFI1_TX_FAULT SFP module Tx status 0b Normal operation default value 1b Transmitter fault 3 XFI1_...

Страница 63: ...ocument USB interface on page 29 Updated Figure 12 on page 30 I2C interface on page 33 Updated CAT24C05 device details in Table 15 I2C bus device map on page 34 Rev 1 03 2017 Board features on page 9...

Страница 64: ...the rights of others NXP sells products pursuant to standard terms and conditions of sale which can be found at the following address nxp com SalesTermsandConditions While NXP has implemented advance...

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