NXP Semiconductors Lite5200B, Руководство пользователя, Страница: 31 / 138

Switches
LITE5200B User’s Manual, Rev. 0
Freescale Semiconductor 4-17
4.6.2 POR
–
SW2
Pressing this switch will initiate a Power-On-Reset.
NOTE
Header J24, which is in parallel with SW2, provides a way for an external
signal to reset the Lite5200B board.
Table 4-25. Boot Configuration Settings
Setting
1
1
Setting denoted by
A
are design time considerations. The Lite5200B will not function if these are changed from
the default configuration.
Options
XLB CLK SEL
*Bit = 0: XLB_CLK = SYS_PLL FVCO/4
Bit = 1: XLB_CLK = SYS_PLL_FVCO/8
SYS PLL CFG
*Bit =0 : SYS_PLL FVCO = 16x SYS_PLL_FREF
Bit =1 : SYS_PLL FVCO = 12x SYS_PLL_FREF
2X FVCO
*Bit = 0: Fvco = 12x or 16x sys_xtal_in (default)
Bit = 1: Fvco = 24x or 32x sys_xtal_in
MOST GRAPHICS
A
*Bit = 0: Most Graphics boot not enabled
Bit = 1: Most Graphics boot enabled.
LARGE FLASH
A
*Bit = 0: Large Flash boot not enabled
Bit = 1: Large Flash boot enabled.
BOOT HIGH
Reset Vector is:
Bit = 0: 0x00000100 (hex)
*Bit = 1: 0xFFF00100 (hex)
WAITSTATES
Bit = 0: 4 IPbus clocks of waitstate*
*Bit = 1: 48 IPbus clocks of waitstate*
BYTE LANE SWAP
A
*Bit = 0: no byte lane swap - same endian ROM image
Bit = 1: byte lane swap - different endian ROM image
WIDE BOOT DATA LANE
A
For “non-muxed” boot ROMs
*Bit = 0: 8-bit boot ROM data bus 24-bit boot ROM address
Bit = 1: 16-bit boot ROM data bus 16-bit boot ROM address
For "muxed" boot ROMs boot ROM addr is max 25 significant
bits during address tenure.
Bit = 0: 16-bit ROM data bus
Bit = 1: 32-bit ROM data bus
For "large flash" boot case boot Flash addr is 25 bits.
Bit = 0: 8-bit Flash data bus
Bit = 1: 16-bit Flash data bus
MUXED BOOT
A
*Bit = 0: non-muxed boot ROM bus, single tenure transfer.
Bit = 1: muxed boot ROM bus,
PPC like with address & data tenures, ALE_b & TS_b active.