NXP Semiconductors Lite5200B, Руководство пользователя, Страница: 137 / 138

LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor Index-7
Rename register operation, 6-15
Reservation station, 6-2
Reserved instruction class, 2-18
Reset
HRESET signal, 7-25
HRESET signal, 8-40
reset exception, 4-17
settings caused by hard reset, 4-17
SRESET signal, 7-25, 8-40
Retirement, definition, 6-2
Rotate and shift instructions, 2-25, A-17
RPA (required physical address), 5-35
RSRV signal, 7-27, 8-41
Run_N counter register, 1-19
S
Segment registers
SR manipulation instructions, 2-45, A-23
T bit, Glossary-4
Segmented memory model, see Memory management
unit
Self-modifying code, 2-29
Serializing instructions, 6-16
Signals
AACK, 7-15
ABB, 7-4, 8-7
address arbitration, 7-2, 8-7
address transfer, 8-11
address transfer attribute, 8-12
A
n , 7-6
APE, 7-8
AP
n , 7-7
ARTRY, 7-15, 8-24
BG, 7-4, 8-7
BR, 7-3, 8-7
checkstop, 8-40
CI, 7-13
CKSTP_IN, 7-24
CKSTP_OUT, 7-24
CLK_OUT, 7-30
configuration, 7-2
COP/scan interface, 7-27
CSE
n , 7-14, 8-29
data arbitration, 8-7, 8-21
data transfer termination, 8-24
DBB, 7-17, 8-8, 8-22
DBDIS, 7-21
DBG, 7-17, 8-7
DBWO, 7-17, 8-7, 8-23, 8-42
DH
n /DL n , 7-18
DPE, 7-20
DP
n , 7-19
DRTRY, 7-22, 8-24, 8-27
GBL, 7-14
HRESET, 7-25
INT, 7-23, 8-40
MCP, 7-24
PLL_CFG
n , 7-30
QACK, 7-26, 8-37, 8-40
QREQ, 7-26, 8-41
reset, 8-40
RSRV, 7-27, 8-41
SMI, 4-33, 7-23
SRESET, 7-25, 8-40
TA, 7-21
TBEN, 7-27
TBST, 7-12, 8-23
TC
n , 7-13, 8-19
TEA, 7-22, 8-24, 8-27
TLBISYNC, 7-27
TS, 7-5
TSIZ
n , 7-12, 8-13
TT n , 7-8, 8-12
WT, 7-14
XATS (603-specific), 1-6
Single-beat reads with data delays, timing, 8-34
Single-beat transactions, 3-8
Single-beat transfer
reads with data delays, timing, 8-33
reads, timing, 8-31
termination, 8-25
writes, timing, 8-32
SMI signal, 4-33, 7-23
Snoop operation, 3-19, 6-23
Split-bus transaction, 8-8
SPR encodings not implemented in 603e, B-2
SRESET signal, 7-25
SRR0/SRR1 (status save/restore registers)
bit settings for machine check exception, 4-10
bit settings for table search operations, 4-10
Stall, definition, 6-3
Static branch prediction, 6-18
Store operations
memory coherency actions, 3-19
single-beat writes, 8-32
String instructions, 2-33, A-20
Superscalar, 6-3
Supervisor mode,
see Privilege levels
Supervisor-level registers summary, 2-4
sync operation, 3-19
Synchronization
context/execution synchronization, 2-20
execution of rfi, 4-14
memory synchronization
instructions, 2-38, 2-40, A-21
SYSCLK signal, 7-29
System call exception, 4-28
System interface