NXP Semiconductors Lite5200B, Руководство пользователя, Страница: 135 / 138

LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor Index-5
integer load instructions, 2-30, A-19
integer store instructions, 2-31, A-20
load/store multiple instructions, 2-32, A-20
memory synchronization
instructions, 2-38, 2-40, A-21
string instructions, 2-33, A-20
Load/store unit
execution timing, 6-22
latency, load and store instructions, 6-31
Logical addresses
translation into physical addresses, 5-1
lwarx / stwcx.
atomic memory references, 3-19
support, 8-41
M
Machine check exception
checkstop state, 4-20
register settings, 4-19
SRR1 bit settings, 4-10
machine check exception enabled, 4-19
MCP signal, 7-24
MEI protocol
definition, MEI states, 3-15
enforcing memory coherency, 8-29
hardware considerations, 3-17
Memory accesses, 8-4
Memory coherency bit (M bit)
cache interactions, 3-10
I-bit setting, 3-12
M-bit setting, 3-12
timing considerations, 6-23
Memory control instructions
segment register manipulation, 2-45
TLB management, 2-45
user-level cache, 2-41, 2-44, 3-22
Memory management unit
address translation flow, 5-11
address translation mechanisms, 5-8, 5-11
block address translation, 5-9, 5-11, 5-20
block diagram, 5-5–5-7
direct address translation, 3-11, 5-9, 5-11, 5-19
exceptions, 5-14
features summary, 5-2
instructions and registers, 5-17
memory protection, 5-10
overview, 1-11, 1-31
page address translation, 5-8, 5-11, 5-27
page history status, 5-11, 5-21–5-24
page table search operation, 5-27
segment model, 5-20
software table search operation, 5-31, 5-36, 5-37
Memory synchronization
instructions, 2-38, 2-40, A-21
stwcx. , 2-38
Memory/cache access modes
performance impact of copy-back mode, 6-23
see also WIMG bits
Misaligned accesses, 2-14
Misaligned data transfer, 8-16
Move instructions, 2-29
MSR (machine state register)
bit settings, 4-11
DR/IR bit, 4-12
EE bit, 4-11
FE0/FE1 bits, 4-13
POW bit, 2-5, 4-11
RI bit, 4-14
settings due to exception, 4-16
TGPR bit, 2-5, 4-11
N
No-DRTRY mode, 8-39
Nondenormalized mode, support, 2-26
O
Operand conventions, 2-13
Operand placement and performance, 2-15
Operating environment architecture (OEA), xxvii,
1-15, 2-42
Optional instructions, A-35
P
Page address translation
page address translation flow, 5-27
page size, 5-20
selection of page address translation, 5-8, 5-14
table search operation, 5-27
TLB organization, 5-25
Page history status
R and C bit recording, 5-11, 5-21–5-24
Page tables
resources for table search operations, 5-31
software table search operation, 5-31, 5-36
table search for PTE, 5-27
Performance considerations, memory, 6-22
Physical address generation
memory management unit, 5-1
PID7v-603e features, 1-4
Pipeline
instruction timing, definition, 6-2
pipeline stages, 6-7
superscalar/pipeline diagram, 6-5
Pipelined execution unit, 6-4
PLL configuration, 7-30
Power management
doze mode, 9-3