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LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor Glossary-7
Normalization. A process by which a floating-point value is manipulated such that it can
be represented in the format for the appropriate precision (single- or
double-precision). For a floating-point value to be representable in the single- or
double-precision format, the leading implied bit must be a 1.
O
OEA (operating environment architecture). The level of the architecture that describes
PowerPC memory management model, supervisor-level registers,
synchronization requirements, and the exception model. It also defines the
time-base feature from a supervisor-level perspective. Implementations that
conform to the PowerPC OEA also conform to the PowerPC UISA and VEA.
Optional. A feature, such as an instruction, a register, or an exception, that is defined by
the PowerPC architecture but not required to be implemented.
Out-of-order. An aspect of an operation that allows it to be performed ahead of one that
may have preceded it in the sequential model, for example, speculative operations.
An operation is said to be performed out-of-order if, at the time that it is
performed, it is not known to be required by the sequential execution model. See
In-order .
Out-of-order execution. A technique that allows instructions to be issued and completed
in an order that differs from their sequence in the instruction stream.
Overflow. An condition that occurs during arithmetic operations when the result cannot be
stored accurately in the destination register(s). For example, if two 32-bit numbers
are multiplied, the result may not be representable in 32 bits. Since the 32-bit
registers of the 603e cannot represent this sum, an overflow condition occurs.
P
Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned
on a 4-Kbyte boundary.
Page access history bits. The changed and referenced bits in the PTE keep track of the
access history within the page. The referenced bit is set by the MMU whenever
the page is accessed for a read or write operation. The changed bit is set when the
page is stored into. See Changed bit and Referenced bit .
Page fault. A page fault is a condition that occurs when the processor attempts to access a
memory location that does not reside within a page not currently resident in
physical memory . On PowerPC processors, a page fault exception condition
occurs when a matching, valid page table entry (PTE[V] = 1) cannot be located.
Page table. A table in memory is comprised of page table entries , or PTEs. It is further
organized into eight PTEs per PTEG (page table entry group). The number of
PTEGs in the page table depends on the size of the page table (as specified in the
SDR1 register).
Page table entry (PTE). Data structures containing information used to translate effective
address to physical address on a 4-Kbyte page basis. A PTE consists of 8 bytes of
information in a 32-bit processor and 16 bytes of information in a 64-bit processor.