NXP Semiconductors Lite5200B, Руководство пользователя, Страница: 127 / 138

LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor Glossary-9
Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the
condition register (CR) to reflect the result of the operation.
Referenced bit. One of two page history bits found in each page table entry . The processor
sets the referenced bit whenever the page is accessed for a read or write. See also
Page access history bits .
Register indirect addressing. A form of addressing that specifies one GPR that contains
the address for the load or store.
Register indirect with immediate index addressing. A form of addressing that specifies
an immediate value to be added to the contents of a specified GPR to form the
target address for the load or store.
Register indirect with index addressing. A form of addressing that specifies that the
contents of two GPRs be added together to yield the target address for the load or
store.
Rename register. Temporary buffers used by instructions that have finished execution but
have not completed.
Reservation. The processor establishes a reservation on a cache block of memory space
when it executes an lwarx instruction to read a memory semaphore into a GPR.
Reservation station. A buffer between the dispatch and execute stages that allows
instructions to be dispatched even though the results of instructions on which the
dispatched instruction may depend are not available.
RISC (reduced instruction set computing). An architecture characterized by
fixed-length instructions with nonoverlapping functionality and by a separate set
of load and store instructions that perform memory accesses.
S
Scan interface. The 603e test interface.
Secondary cache. A cache memory that is typically larger and has a longer access time
than the primary cache. A secondary cache may be shared by multiple devices.
Also referred to as L2, or level-2, cache.
Set ( v ) . To write a nonzero value to a bit or bit field; the opposite of clear . The term ‘set’
may also be used to generally describe the updating of a bit or bit field.
Set ( n ) . A subdivision of a cache . Cacheable data can be stored in a given location in one
of the sets, typically corresponding to its lower-order address bits. Because several
memory locations can map to the same location, cached data is typically placed in
the set whose cache block corresponding to that address was used least recently.
See Set-associative .
Set-associative. Aspect of cache organization in which the cache space is divided into
sections, called sets . The cache controller associates a particular main memory
address with the contents of a particular set, or region, within the cache.