Chapter 9
Peripheral Bridge (AIPS-Lite)
9.1 Chip-specific information for this module
9.1.1 Peripheral slot assignment
The peripheral bridge is used to access the registers of most of the modules on this
device. See
Peripheral Bridge (AIPS-Lite) Memory Map
for the memory slot assignment.
The following table shows the mapping between on/off-platform Peripheral Access
Control Register and Peripheral bridge slot assignment. For example, AIPS_OPACR0 is
correspoding to slot 32 (Flash memory).
Peripheral Access Control Register
Peripheral bridge slot number
AIPS_PACR
n
n
AIPS_OPACR
n
n
+32
9.2 Introduction
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
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