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26
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©
N
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2020
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4.3
For low supply voltage application
– close to 2.0V,
please ensure that the supply track is well
dimensioned so as to avoid IR drop and hence falsely
trigger the brown-out.
(IR drop is the voltage drop due to the supply current
flowing into the supply track resistance).
4.4
Have the VDD lines been isolated from potential
interferences?
4.5
Is GND plane continuous around and near all signals?
4.6
Has the die pad been properly connected to GND?
4.7
Are vias implemented in the die pad?
5
EMC and Misc
5.1
In case more than 2 layers are used, does one layer
act as a continuous ground plane (GND reference
plane)?
5.2
Are numerous vias added near capacitor, near
fingers,…?
5.3
Remove small GND areas and isolated fingers that
cannot be connected to the reference GND plane with
a via.
5.4
Have silk screens been added with relevant
information? (components ref, logo,
board name…)
5.5
Are all silkscreen texts readable when the board is
populated?
5.6
Have traces been avoided below noisy or sensitive
components?
5.7
Check that traces do not cut across power or ground
planes unnecessarily.
5.8
Is the K32W061/041 footprint strictly similar to the
NXP reference?
5.9
If more than 2 layers are used, the inner layers must
be left empty below the RF components and the
antenna
5.10
Each connection between a component and GND
must be doubled with a via to the GND plane.
5.11
Have the soldering/non soldering areas been
respected?
Is solder resist layer check in the empty area?
5.12
If sold unit is a module is a CAN/shield implemented?
