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NXP Semiconductors
JN-RM-2080
K32W module development reference manual
JN-RM-2080
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Reference manual
Rev. 1.0
— 27 Mar 2020
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possible use 2 vias to connect the capacitor to the ground layer.
Best configuration
Wrong configuration:
•
There are not enough vias
•
The vias are too far from the
decoupling capacitors
Fig 10. GND vias placement
The capacitor with a smaller capacitance must be placed nearer to the IC.
The decoupling capacitor must be placed between the main supply line and the supply
pin as shown below:
VDD
Main supply
trace on layer 3
VDD
Gnd
Gnd
Main supply trace
on layer 3
cap
best configuration
via
via
via
via
Wrong configuration:
The decoupling capacitor is not
placed between the main line and
the VDD pin
Fig 11. Decoupling capacitors placement
4.10.2 VDD(RADIO), FB, VDD_PMU, VDDE and VBAT decoupling
Copy as much as possible the placement of the decoupling capacitors of all the supply
pins as shown below.
