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Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
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MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
Freescale Semiconductor
21
Board Control Status Registers (BCSR)
10.6
BCSR5
Table 13. BCSR5 Register
10.7
BCSR6
Table 14. BCSR6 Register description
[7]
CFG_SOURCE
Reset Configuration Source bit lets users select RCW
source.
• 0: RCW is read through I
2
C.
• 1: RCW is read through IO pin sampling.
SW9[8] sampled at
HRESET [
1
]
R/W
Bit
Config Signals
Function
Default
Att
[0:2]
CFG_HOST_AGT[0:2]
MPC8569E configured to act as a host or agent to
another interface master (PEX and SRIO).
SW10[1:3] sampled
at HRESET [
111
]
R,W
[3]
CFG_PLAT_SPEED
Platform speed configuration input configures internal
logic for proper operation with CCB frequencies.
• 0: CCB frequency < 333 MHz
• 1: CCB frequency > or = 333 MHz.
SW10[4] sampled
at HRESET [
1
]
R,W
[4]
CFG_CORE_SPEED
Core speed configuration input configures internal logic
for proper operation with core clock frequencies.
• 0: Core clock frequency < or = to 1000MHz.
• 1: Core clock frequency > 1000MHz.
SW10[5] sampled
at HRESET [
1
]
R,W
[5]
CFG_ELBC_ECC
POR configuration input enables eLBC ECC checking on
booted external local bus interface.
• 0: eLBC ECC disabled after POR.
• 1: eLBC ECC enabled after POR.
SW10[5] sampled
at HRESET [
0
]
R,W
[6]
CFG_FUSE_OVR_DIS
• 0: Fuse PLL override is enabled.
• 1: Fuse PLL override is disabled.
SW10[6] sampled
at HRESET [
1
]
R,W
[7]
CFG_FUSE_READ
Fuse Read Enable
• 0: Fuse reads are disabled during reset sequence.
• 1 (Default): Fuse reads are enabled during reset
sequence.
SW10[7] sampled
at HRESET [
1
]
R,W
Bit
Config Signals
Function
Default
Att
[0]
UPC1_EN
• 1: Enable UPC1, ATM, or POS
• 0: Disable UPC1
OR
enable TDM1A, TDM1B,
TDM1E, TDM1F, TDM1G, TDM1H, TDM2A, TDM2C,
TDM2D, TDM2E, RMII5, RMII7, RMII8, TDM2G,
TDM2F, and RMII6
[1]
R,W
[1]
RUPC1POS_EN
• 1: Enable UPC1POS
• 0: Disable UPC1POS
OR
enable TDM2A and TDM1B
[1]
R,W
Bit
Config Signals
Function
Default
Att
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