Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
Contact us: [email protected] Website: www.integrated-circuit.com
MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
20
Freescale Semiconductor
Board Control Status Registers (BCSR)
10.3
BCSR2
Table 10. BCSR2 Register
10.4
BCSR3
Table 11. BCSR3 Register
10.5
BCSR4
Table 12. BCSR4 Register
Bit
Config Signals
Function
Default
Att
[0:4]
CFG_QE_PLL[0:4]
• A multiplier and divisor, applied to SYSCLK input,
define the QE clock:
– QE Clock=SYSCLK*(CFG QE
PLL[0:4]/CFG_QE_CLK)
SW6[1:5] sampled
at HRESET [
01000
]
R,W
[5]
SDHC
SDHC Card Detect Polarity Select
• 0: SDHC card-detect polarity is inverted.
• 1 (Default): SDHC card-detect polarity isn’t inverted.
SW6[6] sampled at
HRESET [
1
]
R,W
[6:7]
CFG_LVDD_VSEL[0:1]
Voltage Select Dedicated Pins
• QE UCC1 and UCC3 Voltage Select
• QE UCC2 and UCC4 Voltage Select
SW6[6:7] sampled
at HRESET [
11
]
R,W
Bit
Config Signals
Function
Default
Att
[0:3]
CFG_PORT_SEL[0:3]
IO Select Configuration for SerDes.
SW8[1:4] sampled
at HRESET [
0111
]
R,W
[4:6]
CFG_RIO_ID[5:7]
RapidIO Device ID [5:7].
SW8[5:7] sampled
at HRESET [
000
]
R,W
[7]
CFG_RIO_SYS_SIZE
RapidIO System Size
• 0: Large system size with a maximum of 65,536
devices.
• 1: Small system size with a maximum of 256 devices.
SW8[8] sampled at
HRESET [
1
]
R,W
Bit
Config Signals
Function
Default
Att
[0:3]
CFG_ROM_LOC[0:3]
Selects physical location of boot ROM.
SW9[1:4] sampled
at HRESET [
1101
]
R,W
[4]
CFG_BOOT_CPU
Specifies Boot Configuration Mode:
• 0: CPU Boot Hold-off Mode; e500 core boots after
configuration by an external master.
• 1 (Default): e500 core boots without being configured
by an external master.
SW9[5] sampled at
HRESET [
1
]
R,W
[5:6]
CFG_BOOT_SEQ[0:1]
Boot Sequencer
• Allows Boot Sequencer to load serial ROM (on I
2
C1
port) configuration data before the host configures the
MPC8569E.
SW9[6:7] sampled
at HRESET [
11
]
R,W
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