Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
Contact us: [email protected] Website: www.integrated-circuit.com
MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
Freescale Semiconductor
9
Switch Default Settings
SW1 Configuration: SerDes CLK
SW1.1-SW1.4: SerDes Reference Clock
• Sets reference clock value for MPC8569 SerDes module.
• Sets reference clock values for external PEX/SRIO/SGMII interfaces.
• (Default) 100 MHZ and no spread.
SW5 Configuration: DDR3
NOTE!
Switch positions related
to DDR2 usage are
marked with the symbol:
SW5.1- SW5.3: DDR Complex Clock PLL Ratio
• Establish clock ratio between SYSCLK input and DDR complex clock.
SW5.4: DDR PLL Feedback Select
• ‘0’: Local/Shorter feedback path selected
• ’1’: (Default) Longer feedback path selected (matches insertion delay of DDR,QE and
Platform
SW5.5: DDR SDRAM Type
• ‘0’: (Default) DDR3, 1.5V, CKE low at reset.
• ’1’: DDR2, 1.8V, CKE low at reset.
SW5.6: DRAM Mode
• ‘0’: Primary and secondary DDR is enabled (32-bit width data bus).
• ‘1’: (Default) Primary DDR is enabled (64-bit width data bus); secondary DDR is disabled.
SW5.7: DDR Speed
• ‘1’: (Default) DDR clock frequency < 500MHz.
• ‘0’: DDR clock frequency > or = to 500MHz.
SW5.8: Disables DDR2 Phase Reset Logic
• ‘0’: DDR controller disables MCKE at reset; a few cycles later MCK is disabled.
• ’1’: (Default) At reset, DDR controller simultaneously disables MCK and MCKE.
4
3
2
1
ON ’0’
SSC1
SSC0
FSEL1
FSEL0
FSEL0
FSEL1
Q0:Q1
SSC0
SSC1
SPREAD%
0 (ON)
0 (ON)
25 MHz
0 (ON)
0 (ON)
/- 0.25
1 (OFF)
0 (ON)
100 MHz
1 (OFF)
0 (ON)
DOWN -0.5
0 (ON)
1 (OFF) 125 MHz
0 (ON)
1 (OFF)
DOWN -0.75
1 (OFF) 1 (OFF) 25 OMHz
1 (OFF) 1 (OFF)
NO SPREAD
8
7
6
5
4
3
2
1
FIX
SPEED
MODE
TYPE
FB SEL
CLK_PLL2
CLK_PLL1
ON ’0’
CLK_PLL0
Value (Binary)
DDR Complex Clock:
SYSCLK Ratio
000
3:1
001
4:1
010
5:1
011
6:1
100
8:1
101
10:1
110
(Default) 12:1
111
Synchronous Mode*
*Synchronous mode: DDR data rate = CCB clock.
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