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Distributor of NXP Semiconductors: Excellent Integrated System Limited

Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
Contact us: [email protected] Website: www.integrated-circuit.com

MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1

Freescale Semiconductor

Switch Default Settings

SW7 Configuration: CLOCK

SW7.1-SW7.4: CCB Clock PLL Ratio

• System PLL inputs establish the clock ratio between SYSCLK input and the Platform Clock

(CCB) used by MPC8569E.

SW7.5-SW7.7: e500 Core PLL Ratios

• Establish ratio between e500 core and e500 core complex bus (CCB) clocks.

SW7.8: SerDes Reference Clock Configuration

• ‘0’: SerDes expects a 125 MHz reference clock frequency.
• ’1’: (Default) SerDes expects a 100 MHz reference clock frequency.

SRDS REFCLK

CORE_PLL2

CORE_PLL1

CORE_PLL0

SYS_PLL3

SYS_PLL2

SYS_PLL1

ON ’0’

SYS_PLL0

Value (Binary)

CCB Clock:

SYSCLK Ratio

0000

Reserved

0001

Reserved

0010

2:1

0011

3:1

0100

4:1

0101

5:1

0110

6:1

0111

7:1

1000

(Default) 8:1

1001

Reserved

1010

Reserved

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

Value (Binary)

e500 Core:

CCB Clock Ratio

000

4:1

001

9:2 (4.5:1)

010

1:1

011

3:2 (1.5:1)

100

(Default) 2:1

101

5:2 (2.5:1)

110

3:1

111

7:2 (3.5:1)

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Содержание Freescale Semiconductor MPC8569E-MDS-PB

Страница 1: ...d Excellent Integrated System Limited Stocking Distributor Stocking Distributor Click to view price real time Inventory Delivery Lifecycle Information Click to view price real time Inventory Delivery...

Страница 2: ...connecting peripheral devices The MPC8569E MDS PB functions with an integrated development environment IDE such as Freescale s CodeWarrior but instructions for working with the IDE are beyond the scop...

Страница 3: ...as Khen BCSR terminology reference document changes and new photos Bootwiz 21 May 2009 3 0 Vladimir Yukht Hadas Khen Revised content 22 June 2009 3 1 Vladimir Yukht Hadas Khen BCSR changes Table 2 Def...

Страница 4: ...set HW Hardware I2C Inter Integrated Circuit multi master serial computer bus IDE Integrated Development Environment IO Input Output IRSENSE Service Voltage Drop Testing JTAG Joint Test Access Group I...

Страница 5: ...ision Time Protocol QE Quick Engine RC Root Complex RCW Reset Configuration Word REG CFG Configuration Register RGMII Reduced General Media Independent Interface RMII Reduced Media Independent Interfa...

Страница 6: ...or ETH TAP TDM Time Division Multiplexing TRIG OUT Signal Trigger_Out UART Universal Asynchronous Receiver Transmitter UCC Universal Communication Controller UEM Universal Ethernet Module UPC Univers...

Страница 7: ...Modules 1 MPC8569E MDS PB 1 2 UEM 2 3 SRIOx1 2 and plastic screws 2 4 PEXx2 1 and plastic screw 1 5 SRIO_LOOPBACK CARD 2 6 Bootwiz 1 Cables 7 RS 232 standard serial cable with two 9 pin connectors 2...

Страница 8: ...TP112 TP114 TP115 TP109 TP106 R432 R400 R520 R433 R438 R458 R463 R439 R521 R485 R519 R278 R298 1 MP7 MP6 MP5 C497 C496 C355 C261 C323 C268 C233 C379 C270 C367 C192 C264 C232 C239 C238 C420 C244 C245 C...

Страница 9: ...in line package DIP switches see Figure 5 Default DIP switch positions establish MPC8569E MDS PB clock modes see Table 4 NOTE Ensure DIP switches are set according to default values Figure 4 MPC8569E...

Страница 10: ...insertion delay of DDR QE and Platform SW5 5 DDR SDRAM Type 0 Default DDR3 1 5V CKE low at reset 1 DDR2 1 8V CKE low at reset SW5 6 DRAM Mode 0 Primary and secondary DDR is enabled 32 bit width data b...

Страница 11: ...C Card Detect Polarity Select 0 SDHC card detect polarity is inverted 1 Default SDHC card detect polarity isn t inverted SW6 7 QE UCC1 and UCC3 Voltage Select 0 QUICC Engine UCC1 3 GB Ethernet interfa...

Страница 12: ...os Establish ratio between e500 core and e500 core complex bus CCB clocks SW7 8 SerDes Reference Clock Configuration 0 SerDes expects a 125 MHz reference clock frequency 1 Default SerDes expects a 100...

Страница 13: ...SEL0 Value Binary Description SerDes Reference Clock Speed 0000 PCI Express x1 2 5 Gbps Lane A 100 MHz 0001 SRIO1 1x 2 5 Gbps Lane A SRIO2 1x 2 5 Gbps Lane B SGMII x2 1 25 Gbps half speed Lanes E F 10...

Страница 14: ...information from an I2C1 interface ROM a valid ROM must be present 10 Uses extended I2C address mode Boot sequencer is enabled Loads configuration information from an I2C1 interface ROM a valid ROM m...

Страница 15: ...MHz SW10 6 eLBC ECC Enable 0 Default eLBC ECC is disabled after POR 1 eLBC ECC is enabled after POR SW10 7 Fuse PLL Override Disable 0 PLL parameters are controlled by fuse bits 1 Default PLL paramete...

Страница 16: ...f Default OPEN J8 Header Remote ON OFF Default Unassembled J9 Header TEST Default OPEN J10 Header SerDes a Default OPEN J11 Socket System Clock Oscillator 66 67 MHz Default Inserted J12 Socket PTP Cl...

Страница 17: ...NAND Flash Socket located on PS Default Insert NAND Flash device P1 10 pin Header PS ISP Used for PS cntr PLD programming P2 Connector 5V IN power jack MPC8569E MDS PB 5V power jack P3 Socket SD Card...

Страница 18: ...sts the functioning of MPC8569E MDS PB push buttons Table 6 MPC8569E MDS PB Push Buttons Push Button Position Description Default SW2 POWER ON OFF Press SW2 to Power ON OFF all PB components Powered f...

Страница 19: ...DR3 Green DDR3 1 5V voltage supply Board is OFF no power or DDR2 voltage supply D3 DDR2 Yellow DDR2 1 8V voltage supply Board is OFF no power or DDR3 voltage supply D4 ASLEEP Orange MPC8569 HRESET is...

Страница 20: ...nals Function Default Att 0 2 CFG_DDR_CLK_PLL 0 2 Configure DDR PLL ratio SW5 1 3 sampled at HRESET DDR2 100 DDR3 110 R W 3 CFG_DDR_FB_SEL DDR QE and Platform PLL Feedback Select 0 gclk matched long D...

Страница 21: ...d Pins QE UCC1 and UCC3 Voltage Select QE UCC2 and UCC4 Voltage Select SW6 6 7 sampled at HRESET 11 R W Bit Config Signals Function Default Att 0 3 CFG_PORT_SEL 0 3 IO Select Configuration for SerDes...

Страница 22: ...MHz 1 CCB frequency or 333 MHz SW10 4 sampled at HRESET 1 R W 4 CFG_CORE_SPEED Core speed configuration input configures internal logic for proper operation with core clock frequencies 0 Core clock f...

Страница 23: ...uld be 1 AND disable DUART0 and I2C2 bus 0 Enable DUART0 AND disable SD Card nibble mode 0 R W 6 TDM2G UPC1_EN 0 BCSR6 7 disable If bit 1 TDM2G is enabled RMII7 BCSR6 7 should be 0 1 R W 7 RMII7 UPC1_...

Страница 24: ...PIB 0 R W 3 G2DIS_125 1 Disable PHY2 clock_out 125MHz 0 Enable PHY2 clock_out 125MHz 0 R W 4 G2ENA_XC 1 Enable 0 Disable 0 R W 5 CS_NOR 1 Boot from NAND_FLASH 0 Boot from NOR_FLASH 0 R W 6 UEM Marvell...

Страница 25: ...it Config Signals Function Default Att 0 UCC4_GETH 1 Enable UCC4_GETH Use UEM module on PB for RGMII or RTBI 0 Disable UCC4_GETH OR enable UCC4_RMII RMII4 on PIB or TDM1C 1 R W 1 UCC4_RGMII 1 Enable R...

Страница 26: ...gured through BCSR registers 0 R W 1 LED1 1 LED ON 0 R W 2 LED2 1 LED ON 0 R W 3 LED3 1 LED ON 0 R W 4 R_SLEW0 Select slew rate for GETH input clock 0 R W 5 R_SLEW 1 R W 6 SSC0 Select SerDes clock syn...

Страница 27: ...EM ref clk 50MHz 1 R W 6 RESET_PIB 1 RESET RMII PHY TDM framer and or ATM PHY 0 Normal operation for RMII PHY TDM framer and or ATM PHY 0 R W 7 ISOLATE_GPIO 1 For RMII6 and RMII7 operation 0 For UPC1...

Страница 28: ...II6 AND enable RMII6 TDM1C UPC1 Dev2 and UCC3 0 Enable SMII6 and TDM2D SMII unsupported 1 R W 5 SMII8 DIS 1 Enable UCC8 RMII on PIB and TDM1H AND disable SMII8 0 Enable SMII8 SMII unsupported 1 R W 6...

Страница 29: ...ble USB 1 R W 1 RnUSBLOWSPD 1 USB full speed 12Mb s 0 USB low speed 1 5Mb s 0 R W 2 RnUSBVCC 0 USB acts as Device USB powered from an external host Enables RMII6 and TDM1G 1 USB acts as Host USB suppl...

Страница 30: ...ock Allocation Port Size 00000000 1FFFFFFF DDR3 DDR3 Memory Controller MEMC1 512MB 32 00000000 3FFFFFFF MEMC1 Integrated Mode 1GB 64 20000000 3FFFFFFF MEMC2 512MB 32 40000000 7FFFFFFF Reserved 1GB 800...

Страница 31: ...RC Includes the noted modules GETH3 4 UEM SerDes Lane e f SRIOx1 or UEM SGMII mode SerDes Lane a b SRIOx1 SerDes Lane a b PEXx2 1xDDR3 SODIMMx64 or 2xDDR3x32 SODIMM PB powered via P2 by an external 5...

Страница 32: ...default switch settings Section 6 Procedure 3 Check PB default connector settings Section 7 Procedure 4 Establish working environment Section 12 Procedure 5 Insert plastic guide pins into PB 1 Insert...

Страница 33: ...ge follow steps for aligning and connecting the Bootwiz NOTE Freescale s CodeWarrior USB TAP enables CodeWarrior IDE software to work with the PB 1 Align Bootwiz module with its CS facing the board s...

Страница 34: ...SW2 to Power ON NOTE Options 2 through 5 PEX EP board 12V DC power is supplied via the corresponding PEX expansion module power jack a b e f Option 1 Option 2 3 Option 4 5 SGMIIx1 SGMIIx1 SGMIIx1 SGM...

Страница 35: ...ct ETH RJ45 cables to UEM modules a Insert SRIOx1 modules into J10 and J17 stabilize with plastic screws b Insert SRIO loopback into assembled SRIOx1 modules SerDes Option 2 two UEM one PEXx1 x1 mode...

Страница 36: ...ev 3 1 Freescale Semiconductor 35 SerDes Module Set ups SerDes Option 4 two SRIOx1 one PEXx1 x1 mode a Insert SRIOx1 modules into J16 and J7 b Insert SRIO loopback into SRIOx1 modules c Insert PEXx2 i...

Страница 37: ...ated System Limited Datasheet of MPC8569E MDS PB BOARD MOD DEV SYSTEM MPC8569 Contact us sales integrated circuit com Website www integrated circuit com MPC8569E MDS PB Hardware Getting Started Rev 3...

Страница 38: ...ose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation...

Страница 39: ...f MPC8569E MDS PB BOARD MOD DEV SYSTEM MPC8569 Contact us sales integrated circuit com Website www integrated circuit com MPC8569E MDS PB Hardware Getting Started Rev 3 1 38 Freescale Semiconductor Se...

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