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Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
Contact us: [email protected] Website: www.integrated-circuit.com
MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
22
Freescale Semiconductor
Board Control Status Registers (BCSR)
10.8
BCSR7
Table 15. BCSR7 Register description
[2]
RUPC1ADDR_EN
• 1: Enable UPC1ADDR, ATM, or POS
• 0: Disable UPC1ADDR
(Unsupported: SMII8 and SMII6)
[1]
R,W
[3]
RUPC1DEV2
• 1: Enable UPC1DEV2, ATM, or POS
• 0: Disable UPC1DEV2
OR
enable TDM2C and UCC3
[1]
R,W
[4]
SD_CARD_1bit
• 1: Enable SD serial mode
AND
disable I
2
C2
• 0: Disable SD serial mode
AND
enable I
2
C2
[0]
R,W
[5]
SD_CARD_4bits
• 1: Enable SD Card nibble mode (SD_CARD_1bit
should be “1”)
AND
disable DUART0 and I
2
C2 bus
• 0: Enable DUART0
AND
disable SD Card nibble mode
[0]
R,W
[6]
TDM2G
• UPC1_EN = 0(BCSR6[7], disable)
• If bit =1, TDM2G is enabled
• RMII7(BCSR6[7] should be = 0
[1]
R,W
[7]
RMII7
• UPC1_EN = 0((BCSR6[7], disable)
• If bit =1, RMII7 is enabled
• TDM2G(BCSR6[6] should be = 0)
[1]
R,W
Bit
Config Signals
Function
Default
Att
[0]
UCC1_GETH
• 1: Enable UCC1_GETH, RGMII, or RTBI
• 0: Disable UCC1_GETH
OR
enable UCC1_RMII
(RMII1) on PIB
[1]
R,W
[1]
UCC1_RGMII
• 1: Enable RGMII
• 0: Disable RTBI
AND
enable RMII on PIB
[1]
R,W
[2]
UCC1_RTBI
• 1: Enable RTBI
• 0: Disable RGMII
AND
enable RMII on PIB
[0]
R,W
[3]
G1DIS_125
• 1: Disable PHY1 clock_out 125MHz
• 0: Enable
[0]
R,W
[4]
G1ENA_XC
• 1: Enable
• 0: Disable
[0]
R,W
[5]
UCC1/UCC2 GETHRST
• 1: Normal operation
• 0: Reset (nMVRST) Marvel UCC1 and UCC2
[1]
R,W
[6]
BRDWP
• BRD (EEPROM I
2
C Memory): write protected for I
2
C
Flash
• 0: Not protected
[1]
R,W
[7]
BOOTWP
• 1: Not protected.
• Boot write protected
[0]
R,W
Bit
Config Signals
Function
Default
Att
23 / 39
23 / 39