DCDC_REG0[DCDC_LP_DF_CMP_ENABLE] = 1
If the DC-DC mode is Boost mode, it is necessary to set POSLIMIT_BOOST_IN to 0x12 after startup. During startup, this register
is set to a small value to limit voltage spikes and the software application must configure this bit field to the recommended value
to allow higher currents, especially when battery voltage is low.
DCDC_REG1[POSLIMIT_BOOST_IN] = 0x12
The DC-DC recommended software initialization and periodically voltage monitoring flowchart is given below:
Enable DCDC
Module Clock Gating
Set
POSLIMIT_BOOST_IN
to 0x12
Configure DCDC
LoopControl Registers and
DCDC_LP_DF_CMP ENABLE
Configure VDD_1P8
and VDD_1P5 output
targets
Is Boost mode
?
Enable Bandgap 1V
buffer
Measure the
VDCDC_IN with ADC
Measure the 1 V
reference bandgap
with ADC
Calculate VDCDC_IN
using bandgap
reference with 8 mV
LSB resolution
Disable
BATTMONITOR_EN_BATADJ
Update
DCDC_BATTMONITOR_BAT
T_VAL
Enable
BATTMONITOR_EN_BATADJ
Initialize ADC
Initialize Timer
Need to adjust
VBATT_DIV
?
no
no
yes
Adjust
VBATT_DIV_CTRL
yes
Timer periodically runs this portion
Figure 6. Flowchart of DC-DC initialization
The period for the Timer to trigger the measurement of the VDCDC_IN is user controlled and depends on the applications
VDCDC_IN voltage dynamics. Every time the application expects a voltage change, it is recommended to execute the
DCDC_BATTMONITOR_BATT_VAL calibration routine.
It is expected that software monitors the VDCDC_IN periodically, using the SAR ADC, and adjust the DC-DC settings as required
to optimize the performance. Not adjusting the DCDC_BATTMONITOR_BATT_VAL when the VDCDC_IN voltage level has
changed could lead to erratic behavior. The DC-DC does not have a bypass circuit. So when configured for buck or boost, the
controller attempts to regulate the voltage no matter what the level of VDCDC_IN.
There are multiple ways to initialize the DC-DC: the DC-DC SDK (Software Development Kit) drivers (fsl_dcdc.c
and fsl_dcdc.h), direct register accesses, or the connectivity framework drivers. The DC-DC connectivity framework is
contained within the DCDC.c and DCDC.h files. Consider the below code segment from the MCUXpresso DC-DC
connectivity Framework as an example to initialize the DC-DC, Timer, and the ADC to set VDD1P8 to 1.8 V and
NXP Semiconductors
DC-DC converter software setup
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note
8 / 28
