DCDC_REG0[VLPR_VLPW_CONFIG_DCDC_HP] = 0 (To enable pulsed mode on VLPR and VLPW)
DCDC_REG0[VLPS_CONFIG_DCDC_HP] = 0 (To enable pulsed mode on VLPS)
DCDC_REG0[DCDC_LP_DF_CMP_ENABLE] = 1 (Needed configuration to reduce ripple and to avoid voltage falling below
minimum limit)
Application software:
• Stepping must be disabled before entering Pulsed Mode:
DCDC_REG3[DCDC_VDD1P8CTRL_DISABLE_STEP] = 1 and DCDC_REG3[DCDC_VDD1P5CTRL_DISABLE_STEP] = 1
• Call user application low-power mode routine
There is no need to re-enable stepping after leaving Pulsed Mode. If there is a need to change the output voltages; VDD_1P8 and
VDD_1P5, the stepping must be re-enabled.
Consider the below code segment using SDK 2.x, instead of the Connectivity Framework, as an example to set Pulsed Mode when
entering low-power mode.
/** DCDC Low power configuration structure **/
dcdc_low_power_config_t dcdc_Low_Power_Config =
{
.workModeInVLPRW = kDCDC_WorkInPulsedMode,
.workModeInVLPS = kDCDC_WorkInPulsedMode,
.enableHysteresisVoltageSense = true,
.enableAdjustHystereticValueSense = false,
.enableHystersisComparator = true,
.enableAdjustHystereticValueComparator = false,
.hystereticUpperThresholdValue = kDCDC_HystereticThresholdOffset75mV,
.hystereticLowerThresholdValue = kDCDC_HystereticThresholdOffset0mV,
.enableDiffComparators = true,
};
/** Code **/
/** DCDC Low Power Configuration **/
DCDC_SetLowPowerConfig(DCDC, &dcdc_Low_Power_Config);
/**Disable Stepping prior to call low power API **/
DCDC_LockTargetVoltage(DCDC); //disable stepping prior to enter low power mode
/** User Call to enter Low Power mode**/
Here goes the low power routine call
After exiting low-power mode, there is no need to re-enable stepping. Enabling the stepping mode is required during the
application output voltages adjustment.
4.3.2 DC-DC spectral content
Due to DC-DC switching frequencies, as shown in Figure 5, it is expected to have a spectral content of 2 MHz (if using a 32 MHz
reference clock) and its harmonics for continuous mode. Also, for low-power modes (Pulsed Mode), as the DC-DC is turned off
for some time and when the voltage drops to a lower threshold, a 2 MHz burst is generated (assuming a 32 MHz reference clock).
This behavior adds another spectral content for the turn-on and turn-off frequency. That low frequency spectral content depends
on the dynamics of the loading, therefore, for each application, it has a different value.
Consider below chart (not to scale) showing the expected spectral content for DC-DC in pulsed mode.
NXP Semiconductors
DC-DC converter software setup
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note
11 / 28
