• DCDC_REG0[DCDC_PWD_OSC_INT]
This bit enables or disables the DC-DC internal oscillator. Only set this bit (internal oscillator is powered down) when a 32 MHz
crystal oscillator is present. The application must ensure that the external oscillator is always present if decide to turn off the
DC-DC internal oscillator. This internal oscillator is the backup source in case of problems with the external clock.
• DCDC_REG0[DCDC_LP_DF_CMP_ENABLE]
This bit selects either a differential or a common mode comparator to measure the output voltages on pulsed mode. To guarantee
better performance, it is recommended to select the differential comparator.
• DCDC_REG0[DCDC_LP_STATE_HYS_L] and DCDC_REG0[DCDC_LP_STATE_HYS_H]
These two bits select the hysteresis upper and lower limits for pulsed mode, varying from -75 mV to +75 mV of the VDD_1P8 target
value. Selecting a tighter value makes the DC-DC to wake up in a higher frequency, that is, a higher refresh rate when comparing
to a wider value. Decreasing the refresh rate improves DC-DC performance, but increases the ripple.
• DCDC_REG0[HYST_LP_COMP_ADJ], DCDC_REG0[HYST_LP_CMP_DISABLE],
DCDC_REG0[OFFSET_RSNS_LP_ADJ], and DCDC_REG0[OFFSET_RSNS_LP_DISABLE] are factory debug bits that
must be left on reset state value.
• DCDC_REG0[PWD_CMP_OFFSET]
This bit enables the comparator to provide a faster loop response on the DC-DC control module. It is recommended
to be powered on (logic 0) only if a high dynamic load is present, otherwise may be left disabled. When
powered on, it reduces overshoot/undershoot for high dynamic loading. The response time increment gets configure
on DCDC_REG2[DCDC_LOOPCTRL_EN_RCSCALE].
The tradeoff is that it increases the power consumption a little. The ripple is higher when there is no high dynamic loading.
4.5.2 DCDC_REG1
• DCDC_REG1[POSLIMIT_BUCK_IN]
This bit limits the duty cycle of DC-DC converter and it is recommended to leave it with the default reset values.
• DCDC_REG1[POSLIMIT_BOOST_IN]
This bit is used to limit the duty cycle in boost mode, limiting voltage spikes during startup. After DC-DC settles, this bit must
be configured with value 0x12 to allow higher currents for the load. It is recommended not to write values other than 0X12 to
this register.
• DCDC_REG1[DCDC_LOOPCTRL_CM_HST_THRESH]
This bit must be maintained in its reset default state, logic 0.
• DCDC_REG1[DCDC_LOOPCTRL_DF_HST_THRESH]
This bit must be maintained in its reset default state, logic 0.
• DCDC_REG1[DCDC_LOOPCTRL_EN_CM_HYST]
Value of this bit is set to logic 1 after DC-DC startup to guarantee proper operation.
• DCDC_REG1[DCDC_LOOPCTRL_EN_DF_HYST]
Value of this bit is set to logic 1 after DC-DC startup to guarantee proper operation.
4.5.3 DCDC_REG2
• DCDC_REG2[DCDC_LOOPCTRL_EN_RCSCALE]
This bit works in conjunction with DCDC_REG0[PWD_CMP_OFFSET] and determines the response time increment for the loop
control when high dynamic load is present.
• DCDC_REG2[DCDC_LOOPCTRL_HYST_SIGN]
Value of this bit is set to logic 1 after DC-DC startup to guarantee proper operation.
NXP Semiconductors
DC-DC converter software setup
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note
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