32 NED
XCM4040SAT4 UME-0002-04
4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Video(10bit)
From Sensor
-
x
White reference
multipl
Test Pattern
select
Black reference
substract
FPGA Processing block diagram
x
Video(8 or 10bit)
To Channel Link
Driver
Digital Gain
-
Digital Offset
8 or 10bit
select
Output Block
select
In Test Pattern mode, Black / White reference and Digital Gain /Offset w ill be skipped.
Figure 4-3-1 FPGA Processing Block Diagram
4.4 Startup
After turning on, the camera run a startup procedure before it starts getting
images and outputting data.
It takes about four seconds.
The startup procedure is as follows.
(1) The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory. (User
settings if any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
After those sequences, the camera is ready to get images and output data.
4.5 Saving and Loading Camera Settings
The camera settings data is saved in the internal memory (flash memory)
and is loaded from the memory when turning on the power supply or loading
(sending the “rfd” command).
The number of times the flash memory can be rewritten will vary
depending on actual operational conditions. After turning on the power supply,
