1012
Chapter 25
Electrical Specifications
User’s Manual U16580EE3V1UD00
25.4.1 External asynchronous memory access read timing
Table 25-6:
External Asynchronous Memory Access Read Timing
Remarks: 1.
T:
2/f
XX
2.
i:
Number of idle states specified by BCC register
3.
w
AS
: Number of waits specified by ASC register
4.
w
D
: Number of waits specified by DWC1, DWC2 register; w
D
≥
1
5.
w:
Number of waits due to external wait signal (WAIT)
6.
n = 0, 1, 3, 4
Parameter
Symbol
MIN.
MAX.
Unit
Data input set up time (vs. address)
<10>
t
SAID
(2 + w
AS
+ w
D
+ w) T - 30
ns
Data input set up time (vs. RD
↓
)
<11>
t
SRDID
(1.5 + w
D
+ w) T - 30
ns
RD Low level width
<12>
t
WRDL
(1.5 + w
D
+ w) T - 15
ns
RD High level width
<13>
t
WRDH
(0.5 + w
AS
+ i) T - 15
ns
Address, CSn
→
RD
↓
delay time
<14>
t
DARD
(0.5 + w
AS
) T - 20
ns
RD
↑ →
address delay time
<15>
t
DRDA
iT - 2
ns
Data input hold time
(vs. RD
↑
)
<16>
t
HRDID
0
ns
RD
↑ →
data output delay time
<17>
t
DRDOD
(1 + i) T - 15
ns
WAIT set up time
(vs. address)
< 31 >
t
SAW
(1 + w
AS
) T- 30
ns
WAIT high level width
<32>
t
WWH
T - 2
ns
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