NDC BETA LaserMike LaserSpeed Pro 8500-4, Инструкция по эксплуатации, Страница: 222 / 348

7-2 LaserSpeed Pro 8500-4 Instruction Handbook: SSI Communications
7.2 SSI Timing and Data Transmission
The LaserSpeed SSI interface supports basic transmission of a latched output data word, repeated output of
a latched output data word, and recovery from interrupted transmission cycles.
The SSI interface operates as a state machine within the LaserSpeed FPGA. The state machine enters its
LATCHDATA state when the master device holds the clock output high for longer than the LaserSpeed trans-
fer timeout
tm
. When in the LATCHDATA state the LaserSpeed updatea the SSI output latch with the latest
measurement value. LaserSpeed 8500/9500 measurement values are internally updated at the start of each
1ms core period. The LaserSpeed data output is always held high when in the LATCHDATA state.
As the master clock makes its first transition from high-to-low
1
, the LaserSpeed transitions to the TRANSFER
state where updates to the latched output word are prevented until a subsequent transfer timeout occurs.
While in the TRANSFER state, the LaserSpeed outputs one bit of the latched data value on each rising edge
2
of the master clock starting with the most-significant bit (msb). For a data payload length of n bits, n+1 rising
clock edges from the master are required to complete the transmission. On the n+1 rising clock edge from
the master
3
the LaserSpeed output is taken low and the LaserSpeed transitions to the LATCHDATA state at
the end of the transfer timeout
tm
.
Basic transmission cycle
The repeated transmission cycle is similar to the basic transmission except that if the master continues to
send clock pulses beyond the required n+1 rising-edges for complete transmission of the latched output pay-
load, the latched output payload is repeated again starting with the msb. The LaserSpeed remains in the
TRANSFER state until the master clock remains idle for the transfer timeout
tm
period of the LaserSpeed.