Table 10. Signal Description of the LED Component (Continued)
Signal Name Direction
Explanation
Clk
In
Stable clock provided by the CPLD. It expects a 40 MHz clock.
cRdyRst
In
Ready/Rst signal. If RdyRst is low, the state of the LED is Power
solid green and Ready off.
cRegPortOut Out
Signals to the EdBlock register port.
cRegPortIn
In
Signals from the EdBlock register port.
cReadyRed
Out
Connects to the Ready red anode.
cReadyGreen Out
Connects to the Ready green anode,
cPowerRed
Out
Connects to the Power red anode.
cPowerGreen Out
Connects to the Power green anode.
Instantiating the LEDs Component
You can instantiate the LEDs component as follows:
Creating Registers
Read and write registers can easily be implemented using the EdBlock register interface by
invoking the RegisterRead and RegisterWrite functions defined in the
PkgEdBlock.vhd
file.
These two functions have the following signatures:
Function
Signature
RegisterWrite RegisterWrite(<Register Address (natural)>,
cRegPortOut)
RegisterRead
RegisterRead(<Register Address (natural)>,
cRegPortOut)
Both functions will return a Boolean value. This value is true if the command in the incoming
master packet matches the function and if the address in the master packet matches the address
20
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SLSC-12101 User Guide