Table 4. Register Descriptions
Register Name
Address
Type
Explanation
Output
kAddress
R/W The value of this register defines the output state
when the corresponding direction bit is set as output
(1).
Direction
kA 1 R/W For each pin of the port, 1 configures the pin as an
output and 0 configures the pin an input.
Input
kA 2 R
Mirrors the state of the external pin for read.
Table 5. Signal Descriptions
Signal Name Direction
Explanation
Generics
kAddress
N/A
Defines the base address of the block. This address will also
correspond to the Output register. The next two consecutive
addresses are assigned to Direction and Input.
kPortSize
N/A
Determines the number of I/O implemented. Acceptable values go
from 1 to 64.
Signals
aReset
In
Board Reset Signal
Clk
In
Stable clock provided by the CPLD.
caIoPort
In/Out
Digital input/output.
cRegPortOut Out
Signals to the EdBlock Register Port.
cRegPortIn
In
Signals from the EdBlock Register Port.
I/O Port Instantiation
You can instantiate the I/O Port block in your design as follows:
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SLSC-12101 User Guide