4-6
|
ni.com
Chapter 4
Digital Input/Output and PFI
Routing DI Reference Trigger Signal to an Output Terminal
You can route DI Reference Trigger to any output PFI terminal. Reference Trigger is active high
by default.
DI Pause Trigger Signal
You can use the DI Pause Trigger (di/PauseTrigger) signal to pause and resume a measurement
acquisition. The internal sample clock pauses while the external trigger signal is active and
resumes when the signal is inactive. You can program the active level of the pause trigger to be
high or low.
Using a Digital Source
To use DI Pause Trigger, specify a source and a polarity. The source can be either from PFI or
one of several other internal signals on your cDAQ chassis. Refer to the
Device Routing in MAX
topic in the
NI-DAQmx Help
or the
LabVIEW Help
for more information.
Using an Analog Source
Some C Series I/O modules can generate a trigger based on an analog signal. In NI-DAQmx, this
is called the Analog Comparison Event.
When you use an analog trigger source, the internal sample clock pauses when the Analog
Comparison Event signal is low and resumes when the signal goes high (or vice versa).
Note
Depending on the C Series I/O module capabilities, you may need
two modules to utilize analog triggering.
Note
Pause triggers are only sensitive to the level of the source, not the edge.
Digital Input Filters
When performing a hardware timed task, you can enable a programmable debouncing filter on
the digital input lines of a parallel DIO module. All lines on a module must share the same filter
configuration. When the filter is enabled, the chassis samples the inputs with a user-configured
Filter Clock derived from the chassis timebase. This is used to determine whether a pulse is
propagated to the rest of the system. However, the filter also introduces jitter onto the input
signal.
In NI-DAQmx, the filter is programmed by setting the minimum pulse width,
Tp
1
, that will pass
the filter, and is selectable in 25 ns increments. The appropriate Filter Clock is selected by the
driver. Pulses of length less than 1/2
Tp
will be rejected, and the filtering behavior of lengths
between 1/2
Tp
and 1
Tp
are not defined because they depend on the phase of the Filter Clock
relative to the input signal.
1
Tp
is a nominal value; the accuracy of the chassis timebase and I/O distortion will affect this value.