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5-7
Writing a VHDL Wrapper Around the Protocol IP Core
A VHDL wrapper is generally necessary to adapt the protocol signals to the dataflow semantics
used within the LabVIEW FPGA diagram. NI recommends that you adhere to the following
guidelines when writing a VHDL wrapper around the protocol IP core:
•
Keep the interface between the CLIP and the LabVIEW FPGA diagram as simple as
possible.
Note
LabVIEW stores values in big-endian format, and your IP may accept only
little-endian format. NI recommends performing any conversions in the CLIP and
keeping endian conversions off the LabVIEW diagram for ease of use.
•
Do not pass asynchronous signals to the LabVIEW FPGA diagram. Register the signals in
a clock domain in the VHDL logic before passing them to the LabVIEW FPGA diagram.
•
Use AXI4-Stream and AXI4-Lite interfaces for streaming data and register accesses.
NI provides AXI4-Stream and AXI4-Lite wrappers to use on the LabVIEW FPGA
diagram. Refer to the
Generating an IP Core from the Xilinx Vivado IP Catalog
section of
this document for more information about IP core logic.
•
If you expose an AXI4-Lite endpoint, use Xilinx AXI4 interconnect IP to expose only
one AXI4-Lite endpoint to the LabVIEW FPGA diagram.
•
Document the frequency of clocks coming from CLIP. Consider supporting enable chain
removal.
•
Implement a state machine that allows asynchronous resets. If you declare an input signal
as a reset signal in the CLIP wizard, then that signal is asserted when the LabVIEW FPGA
VI is not running.
•
Implement a state machine that resets the protocol cores when the
PORT#
module is absent
if your state machine does not already account for this.
•
Connect various clocks from your CLIP to the DebugClks std_logic_vector in order to use
host-side frequency counter debugging utilities.
•
Provide timing constraints in XDC for your CLIP. Include timing constraints for clocks
within your CLIP, but do not include pin/location constraints on MGTs transceiver lanes
and RefClks. Refer to
UG 903: Vivado Design Suite User Guide: Using Constraints
at
xilinx.com
for more information about timing constraints in XDC for your CLIP.
•
Use the TXOUTCLK and/or RXOUTCLK clock constraints for your high-speed serial
CLIP if your protocol uses it directly.
–
The following is an example syntax for the constraint:
create_clock -period
<period in ns> [get_pins %ClipInstancePath%/<path to your
clock pin relative to the top level CLIP VHDL>]
.
