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4-7
DMA Streaming
The NI-793xR devices support both host-to-target streaming and target-to-host streaming
through DMA channels that connect the host to your target. Use DMA streaming to allow the
maximum throughput of data from your host application to be streamed to the target at high rates
of speed.
The NI-793xR provides up to 16 DMA channels that can be accessed by your Host. These
channels can be used in a variety of ways to meet your application’s needs. The total overall
bandwidth of the device limits your DMA use, whether you use 1 DMA channel or 16.
The maximum width of a DMA channel is 256 bits. To use the full width of the DMA channel
to achieve maximum throughput, create a data construct that matches the 256-bit data width of
the DMA channel. You can either create a cluster that contains 4 U64s, or an array of 4 U64s.
To use an array, the FIFO must be configured to return multiple elements per read/write. You can
also write up to 1,024 bits at a time from LabVIEW FPGA, and the Ready for Input connection
throttles the connection to the FIFO to prevent overflow.
Theoretically, DMA throughput is maximized and is most consistent when the DMA FIFO
buffer is sized as large as possible to absorb variations in the readiness of the host memory.
However, sizing the FIFO larger consumes block RAM resources on the FPGA and increases
the timing pressure on the FIFO. NI recommends making the FIFO as large as you can
successfully compile with, in order to sustain throughput through the PCIe bus to and from host
memory. You can change the size of the FIFO by configuring the Requested Number of
Elements for the FIFO in the project properties. You can validate the DMA sizing through
benchmarking, and you can use VIs in the Streaming Design Library to monitor the health of a
FIFO.
For more detailed information about using DMA, DMA best practices, and how to make design
decisions on how to implement DMA in your application, refer to the
Transferring Data Using
Direct Memory Access
topic of the
LabVIEW FPGA Help
.
Total throughput depends on the SCTL rate from the FPGA that is reading or writing the DMA
channels. The data throughput is calculated by the following equation:
(Data Width × Samples per Cycle) × Number of DMA FIFOs × SCTL Clock Rate =
Data Throughput
Note
The total data throughput cannot exceed the maximum data specification for
your device. Refer to the Specifications document for your device for information
about data throughput limits.
Note
The number of array elements fed into the DMA FIFO from the Host can limit
the maximum throughput for your application. Use large array subsets and set your
FIFO depths to be deep enough to sustain high throughput.
