MS-9156 ATX Server Board
3-14
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [By SPD] enables DRAM timing to
be determined automatically by BIOS based on the configurations on the SPD.
Selecting [Manual] allows users to configure these fields manually.
CAS Latency Time
This controls the timing delay (in clock cycles) before SDRAM starts a read
command after receiving it. Settings: [1.5], [2], [2.5] (clocks). [1.5] (clocks)
increases the system performance the most while [2.5] (clocks) provides the
most stable performance.
Active to Precharge Delay
The field specifies the idle cycles before precharging an idle bank.
DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay between the
CAS and RAS strobe signals, used when DRAM is written to, read from or
Advanced Chipset Features
MSI Reminds You...
Change these settings only if you are familiar with the chipset.
