Flash Memory
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periodically to keep it from expiring. Following reset, the watchdog timer
is disabled.
The watchdog timer has two output pins, WDNMI and WDE. The
WDNMI is asserted after the timer is enabled and the 24-bit NMI_VAL
count is reached. The WDNMI pin is connected to one of the GT-64260B
interrupt input pins so that an interrupt is generated when the NMI_VAL
count is reached. The WDE pin is asserted after the watchdog timer is
enabled and the 32-bit watchdog count expires. The WDE pin is connected
to the board reset logic so that a board reset is generated when WDE is
asserted. For additional details, refer to the GT-64260B System Controller
for PowerPC Processors Data Sheet, listed in
Flash Memory
The MVME5500 contains two banks of Flash memory accessed via the
device controller contained within the GT-64260B. The standard
MVME5500 product is built with the 128Mb devices.
System Memory
System memory for the MVME5500 is provided by one to four banks of
ECC synchronous DRAM in two banks. During system initialization, the
firmware determines the presence and configuration of each memory bank
installed by reading the contents of the serial presence detection (SPD)
EEPROM on the board, and another one on the expansion memory
module. The system firmware then initializes the GT-64260B memory
controller for proper operation based on the contents of the serial presence
detection EEPROM.
Note
If a PMC module is plugged into PMC slot 1, the memory
mezzanine card cannot be used because the PMC module covers
the memory mezzanine connector.
