1-14
Literature Center Web Site
Hardware Preparation and Installation
1
CPU COP Enable Header (J20)
A 2-pin planar header enables the Riscwatch capability. No jumper
installed disables COP and enables boundary scan. A jumper across pins
1-2 enables the COP emulator debug.
PCI Bus 0.0 Speed Header (J25)
A 2-pin planar header that can force PCI bus 0.0 to run at 33 MHz rather
than the standard method of allowing the PMC board to control whether
the bus runs at 33 MHz or 66 MHz. No jumper installed allows the PMC
board to choose the PCI 0.0 bus speed. A jumper installed across pins 1-2
forces PCI bus 0.0 to run at 33 MHz.
1
2
Enables COP
J20
(factory configuration)
1
2
J20
emulator debug
Disables COP;
enables boundary scan
1
2
PMC board controls
J25
(factory configuration)
1
2
J25
Force PCI bus 0.0
PCI 0.0 bus speed
to run at 33 MHz