Memory Controller Interface
http://www.motorola.com/computer/literature
4-5
4
Memory Controller Interface
The GT-64260B can access up to four banks of SDRAM for a total of 1GB
of SDRAM memory. The memory bus is capable of operating up to
133 MHz.
The MVME5500 board has two banks on board and a connector for an
expansion mezzanine board with two additional banks.
Interrupt Controller
The MVME5500 uses the interrupt controller integrated into GT-64260B
to manage the GT-64260B internal interrupts, as well as the external
interrupt requests. The external interrupt sources include the following:
❏
On-board PMC interrupts
❏
LAN interrupts
❏
VME interrupts
❏
RTC interrupt
❏
Watchdog timer interrupts
❏
Abort switch interrupt
❏
External UART interrupts
The interrupt controller provides up to seven interrupt output pins for
various interrupt functions. For additional details regarding the external
interrupt assignments, refer to the MVME5500 Single-Board Computer
Programmer’s Reference Guide.
I2C Serial Interface and Devices
A two-wire serial interface for the MVME5500 board is provided by a
master/slave capable I2C serial controller integrated into the GT-64260B
device. The I2C serial controller provides two basic functions. The first
function is to optionally provide GT-64260B register initialization
following a reset. The GT-64260B can be configured (by setting jumper
J17) to automatically read data out of a serial EEPROM following a reset
