Block Diagram
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3-11
3
Programmable Timers
Among the resources available to the local processor are a number of
programmable timers. Timers and counters on the MCP750 are provided
by the Raven ASIC, the M48T559, the PBC, and the Z8536 CIO device
(diagrammed in
Figure 1-1
). They can be programmed to generate periodic
interrupts to the processor.
Raven General Purpose Timers
The Raven ASIC contains four 32-bit general purpose timers. Each timer
is driven by a divide-by-eight prescaler which is synchronized to the PPC
processor clock. For a 66.66MHz system, the timer frequency would be
8.25MHz. Each timer may be programmed to generate an MPIC interrupt.
Raven Watchdog Timers
The Raven ASIC contains two Watchdog timers, WDT1 and WDT2. Each
timer is functionally equivalent but independent. These timers will
continuously decrement until they reach a count of 0 or are reloaded by
software. The timeout period is programmable from 1 microsecond up to
4 seconds. If the timer count reaches 0, a timer output signal will be
asserted. The output of Watchdog Timer 1 is routed to generate an MPIC
interrupt. The output of Watchdog Timer 2 is logically ORed onboard to
provide a hard reset.
Following a device reset, WDT1 is enabled with a default timeout of 512
milliseconds and WDT 2 is enabled with a default timeout of 576
milliseconds. Each of these signals is typically delayed an additional 4.8
seconds (2 seconds minimum) using logic external to Raven. Each timer
must be disabled or reloaded by software to prevent a timeout. Software
may reload a new timer value or force the timer to reload a previously
loaded value. To disable or load/reload a timer requires a two step process.
The first step is to write the pattern $55 to the timer register key field which
will arm the timer register to enable an update. The second step is to write
the pattern $AA to the key field along with the new timer information.
During the power-up configuration of the Raven ASIC, PPCBug disables
the two Watchdog timers.
