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Functional Description
3
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Edge/level control for ISA interrupts
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Seven independently programmable DMA channels
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Three interval counters/timers (82C54 functionality)
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I
2C
interface via software programmable GPIO port
Accesses to the configuration space for the PBC are performed by way of
the CONADD and Configuration Address and Data (CONDAT) registers
in the Raven bridge controller ASIC. The registers are located at offsets
$CF8 and $CFC, respectively, from the PCI I/O base address.
Real-Time Clock/NVRAM/Watchdog Timer Function
The MCP750 employs an SGS-Thomson surface-mount M48T559 RAM
and clock chip to provide 8KB of non-volatile static RAM, a real-time
clock, and a watchdog timer function. This chip supplies a clock,
oscillator, crystal, power failure detection, memory write protection, 8KB
of NVRAM, and a battery in a package consisting of two parts:
❏
A 28-pin 330mil SO device containing the real-time clock, the
oscillator, power failure detection circuitry, timer logic, 8KB of
static RAM, and gold-plated sockets for a battery
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A SNAPHAT battery housing a crystal along with the battery
The SNAPHAT battery package is socket mounted on top of the M48T559
device. The battery housing is keyed to prevent reverse insertion.
The clock furnishes seconds, minutes, hours, day, date, month, and year in
BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day
months are made automatically. The clock generates no interrupts.
Although the M48T559 is an 8-bit device, 8-, 16-, and 32-bit accesses from
the ISA bus to the M48T559 are supported. Refer to the MCP750
Programmer’s Reference Guide (MCP750/PG) and to the M48T559 data
sheet for detailed programming and battery life information.
