Block Diagram
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CompactPCI Interface
The CompactPCI bus interface will support up to 7 CompactPCI
peripheral cards. The CompactPCI bus interface is provided using the
DEC 21154 PCI-to-PCI bridge chip. This device implements a 64-bit
primary data bus and 64-bit secondary data bus interface and is PCI 2.1
compliant. The 21154 provides read/write data buffering in both
directions.
The device has an internal arbiter which implements a programmable 2-
level rotating algorithm for all CompactPCI masters. The arbiter latency is
typically one PCI clock. If the 21154 detects that an initiator has failed to
assert FRAME# within 16 clock of the grant, the arbiter will negate the
grant. The arbiter parks the CPCI bus at the last bus master by keeping the
last grant asserted until a new bus request is asserted. After a reset, the
21154 parks the CPCI bus at itself until a new request is asserted.
The 21154 provides the 33MHz clocks for each of the CompactPCI slots.
All clock source outputs are active following power-up or reset. The 21154
provides a control register to allow individual clock sources to be disabled.
For additional information, refer to the DEC21154 data sheet.
The 21154 supports 3.3V or 5V signalling at the PCI busses with a separate
VIO pin for the primary and secondary bus buffers. The primary bus
signalling voltage is tied to +5 volts. The secondary bus signalling voltage
is tied to the CPCI bus VIO, so the MCP750 is a universal board that may
operate in a +3.3V or +5V chassis.
Ethernet Interface
The MCP750 module uses Digital Equipment’s DECchip 21140 PCI Fast
Ethernet LAN controller to implement an Ethernet interface that supports
10/100 Base-T connections. The balanced differential transceiver lines are
coupled via on-board transformers.
The MCP750 routes its 10/100 Base-T lines to an RJ45 connector on the
front panel.
