Index
IN-2
Computer Group Literature Center Web Site
I
N
D
E
X
COM1
1-26
COM1 port
as part of Super I/O device
3-8
COM1 restrictions
1-11
COM1 signal routing
1-11
COM2 port
as part of Super I/O device
3-8
commands
5-6
commands, debugger
5-7
Compact FLASH
installation
1-16
location
1-16
CompactPCI Bus
as reset source
2-7
CompactPCI bus capacity
3-5
conductive chassis rails
A-3
configuration
transition module, serial port 3 & 4
1-11
configuration, I/O
1-3
,
1-9
configure
PPC1Bug parameters
6-3
Configure Board Information Block (CNFG)
6-1
connector
10BaseT/100BaseT
4-11
DB9
3-8
for backplane expansion
4-6
for COM1 port
4-12
for I/O routing
4-4
for peripherals
4-7
J3 I/O
3-8
connector pin assignments
4-1
connectors (baseboard)
corresponding to PMC connectors
1-22
control signals
support for
3-13
cooling requirements
A-2
counters
3-11
CPCI activity LED
3-18
CPU activity LED
3-18
CPU Type register
2-4
CTS
support for
3-13
D
DB9 connector
1-11
,
3-8
DCD
support for
3-13
debug firmware, PPCBug
5-1
debugger
directory
5-14
prompt
5-2
debugger command
parts of
5-6
debugger commands
5-7
debugger console port
1-26
debugger firmware
2-1
,
3-20
debugger firmware (PPCBug)
6-1
DEC 21140 LAN controller
as bus master
2-5
DEC 21154 function
3-5
DECchip 21140 LAN controller
3-5
DECchip 21154
PCI-to-PCI bridge
2-5
default map
PCI/ISA I/O
2-4
default memory map
defined
2-3
devices
access mechanism
2-5
affected by various resets
2-8
configuring on PCI bus
2-5
diagnostics
directory
5-14
hardware
5-13
prompt
5-2
test groups
5-14
directories, debugger and diagnostic
5-14
disk drive
controller
3-7
disk drive controller
as interface to ISASIO
3-8
compatibility
3-9
DMA channels