Motorola MC68360, Руководство пользователя

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14 MC68360 USER’S MANUAL ERRATA MOTOROLA
27. Typo on Table 7-11.
On page 7-248, the last three entries of Table 7-11 were mistyped.The correct entries are:
28. Missing Bit in Ethernet Receive Buffer Descriptor.
On page 7-260, the figure of the receive buffer descriptor is not correct. The correct figure is
:
29. Replace the DEF Explanation.
On Page 7-263, section 7.10.23.19, the DEF—Defer Indication explanation should be
replaced with the following paragraph:
This frame was deferred before being successfully sent. Deferral means that the the
transmitter had to wait for carrier sense before sending because the line was busy. This is
not an indication of a collision; collisions are indicated in the Retry Count (RC).
30. Additional Information on Using TSA for Synchronization.
On Page 7-296, section 7.11.10.7, the second paragraph from the bottom is not sufficient
and should be replaced with the following paragraph:
Once the TEN bit is set in SMCMR, the SMC waits for the transmit FIFO to be loaded before
attempting to achieve synchronization. Once the transmit FIFO is loaded, synchronization
and transmission begin according to the following conditions.
If a buffer is made ready when the SMC is enabled, then the first byte will be placed in time
slot 1 if CLSN is set to 8 and slot 2 if CLSN is set to 16.
If a buffer has its SMC is enabled, then the first byte in the next buffer can appear in any time
slot associated with this channel.
If a buffer is ended with the L-bit set, then the next buffer can appear in any time slot
associated with this channel.
SCC Base + 9E TADDR_H Word Temp Address (LSB)
SCC Base + A0 TADDR_M Word Temp Address
SCC Base + A2 TADDR_L Word
Temp Address (MSB)
2
0 E — W I L F — M — — LG NO SH CR OV CL
2 DATA LENGTH
4 RX DATA BUFFER POINTER
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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