6
MC68360 USER’S MANUAL ERRATA
MOTOROLA
4. Typo on Reset Status Register.
On page 6-34, section 6.9.3.3, the 2nd bit of the register should be a reserved bit, not LOC.
Also the description of LOC in the following page should be removed.
5. Typo on SYPCR.
On page 6-35, section 6.9.3.5, the reset value for bits SWT1 and SWT0 were wrong. The
correct value for both bits is MODCK1.
6. Typo on PITR.
On page 6-36, section 6.9.3.7. The reset value for bits SWP and PTP were wrong. The
correct value for both bits is MODCK1.
7. Error in Text.
On page 6-36, section 6.9.3.5, the word EXTALDIV should be replaced with SPCLK.
8. Typo on Register Default.
On page 6-37, section 6.9.3.5, the description for DBFE and BME was not correct. The
correct descriptions are as follows:
DBFE—Double Bus Fault Monitor Enable
0 = Disable the double bus fault monitor function. (Default)
1 = Enable the double bus fault monitor function.
For more information, see 6.3.1.2.3 Double Bus Fault Monitor and Section 5 CPU32+.
BME—Bus Monitor External Enable
0 = Disable bus monitor function for the external bus cycles. (Default)
1 = Enable bus monitor function for the external bus cycles.
For more information see 6.3.1.2.1 Bus Monitor.
9. Typo on BKCR.
On page 6-47, section 6.9.3.13, the following statement, “NEG is ignored if the MA bits are
00" where NEG bit is described is not correct and should be removed.
10. Addition of note on External master support.
On page 6-57, section 6.11.7, the following note should be added after the first paragraph.
NOTE
The MC68EC040 and MC68040 type master is not supported
when the QUICC is configured to a master mode.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
