16
MC68360 USER’S MANUAL ERRATA
MOTOROLA
2. Inconsistent text in Clocking strategy.
On page 9-3, section 9.1.1.2. The paragraph describes the clocking strategy using a
32.768KHz crystal where the Figure 9-1 shows a 25MHz crystal oscillator set up.
To be consistent the following text should replace the text of section 9.1.1.2.
9.1.1.2 Clocking Strategy.
In this application, the system clock is generated from a 25MHz crystal oscillator
output into the QUICC. The QUICC's internal phase-locked loop (PLL) locks to
the input, multiplies the frequency by one, and uses the 25 MHz as the result sys-
tem frequency. The PLL also multiply the clock by two and outputs a 50 MHz sig-
nal on CLKO2. Neither CLKO pin is required for the application. It is
recommended that the CLKO outputs be disabled in software to save power.
The use of a 25MHz crystal oscillator is not a requirement in the application. A
4-MHz crystal or a 32.768-kHz crystal could have been used, if desired. (See
section 6.5 for notes on crystal use.)
The QUICC clocking section allows for the clock oscillator to be kept running
through the VDDSYN pin in a power-down situation. This section does not
address low-power issues, however.
3. Typo on Configuring the Memory Controller.
On page 9-11, section 9.1.3.2, the first statement on page 9-12:
“NCS should normally be cleared”
This should be:
“NCS should normally be set”
4. Error in text.
On page 9-13, the first sentence “To configure the QUICC for 16 bit data bus...” Should be
replaced with “User should drive the 16BM pin when the QUICC™ is in reset. User should
NOT simply tie 16BM to RESETH/RESETS since PRTY3 and PRTY2 pins will be driven the
QUICC even though there are not applicable to the current bus size.
5. MC68040 Companion Mode Bus Cycle Note.
On page 9-31, section 9.4, add the following note:
NOTE
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
