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12

MC68360 USER’S MANUAL ERRATA

MOTOROLA

17. Missing Note on Transmission on Demand.

One page 7-121, section 7.10.5, the following note should be added at the bottom of the
page:

The first bit of the frame will typically be clocked out 5-6 bit times after TOD has been set to
one.

18. Missing Last Step for SCC Initialization.

One page 7-129, section 7.10.9, add the following last step when initializing an SCC:

15. Setup buffer descriptors including control bits as required by the respective protocol ;
clear status bits by writing with zero.

19. Missing Note on Disable Receiver while Transmitting.

On page 7-158, the following note should be added after the description of DRT bit:

User should set the preamble bit in the transmit buffer descriptor if the QUICC™ is being
used in multi-drop UART mode.

Also on page 7-158, the following note should be added after the description of SYN
(Synchronous Mode) bit.

NOTE.

RINV bit in the GSMR must be cleared if synchronous UART
mode is selected.

20. Missing bits in HDLC mode register.

On page 7-178, the following bit definition was missing from the manual.

Bit 2 – BPM (HDLC BUS Priority Mode)

This bit determines the number of idle bits needed to be counted prior to a frame trans-
mission after a successful transmission.

0 = 10 bits
1 = 9 bits

Bit 1 – BCM (HDLC BUS Collision Sense Mode)

This bit determines the sample point of collision detection.

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Содержание MC68360

Страница 1: ...1 the signal names in the left column had a typo The corrections for the typo are in the right column As seen on page 2 2 Correction A31 A27 WE3 WE0 A31 A27 WE0 WE3 SDACK2 L1TSYNCB CTS3 PC8 SDACK2 L1TSYNCB CTS3 PC8 L1RSYNB CD3 PC9 L1RSYNB CD3 PC9 SDACK1 L1TSYNCA CTS4 PC10 SDACK1 L1TSYNCA CTS4 PC10 L1RSYNCA CD4 PC11 L1RSYNCA CD4 PC11 2 Error on TRIS On page 2 4 Table 2 1 the function description of...

Страница 2: ... data BDs This is not true The address range 700 7FFF can be used for User data BDs but address range 800 BFFF is reserved 2 Missing Underline in Table On pages 3 5 through 3 10 Tables 3 3 and 3 4 the following entries should have been underlined RSR CSR1 SDSR CSR2 CIPR CISR TER1 TER2 TER3 TER4 SCCE1 SCCE2 SCCE3 SCCE4 SMCE1 SMCE2 SPIE 3 Missing Bold face in Table On pages 3 5 through 3 10 Tables 3...

Страница 3: ... ramp up time of Vcc never be faster than 4mSec to ensure proper power on reset sequence This restriction has been removed and the note should be deleted NOTE for Rev C 0 Due to a problem with Revision C 0 of the QUICC masks 0E63C and 0F15W a 4ms minimum Vcc ramp up specification was added Characterization of Revision C 1 QUICCs masks 1E68C and 0E68C has demonstrated that this specification is no ...

Страница 4: ...cription of these special situations 6 5 1 2 Using Crystal as Input Clock The 68360 has the ability to use a low speed crystal as its clock source The on chip PLL can multiply the output of the crystal circuit up to the final system frequency A crystal circuit consists of a parallel resonant crystal two capacitors and two resistors Example values for both a 32kHz crystal and a 4MHz crystal are sho...

Страница 5: ...at the MODCK1 0 pins have an internal pullup during reset This is not correct and the sentence should be removed 3 Missing Text On page 6 30 section 6 9 3 1 the note SUPERVISOR ONLY should appear below the MCR register EXTAL CRYSTAL OSCILLATOR XTAL XFC PIN VCCSYN XFC 390nF 0 01 µF 0 1 µF NOTE 1 Must be low leakage capacitor See Section 10 Electrical Characteristics for recommended values 2 Values ...

Страница 6: ...ouble Bus Fault Monitor Enable 0 Disable the double bus fault monitor function Default 1 Enable the double bus fault monitor function For more information see 6 3 1 2 3 Double Bus Fault Monitor and Section 5 CPU32 BME Bus Monitor External Enable 0 Disable bus monitor function for the external bus cycles Default 1 Enable bus monitor function for the external bus cycles For more information see 6 3 ...

Страница 7: ...the assertion and negation of the CAS signal on DRAM page hit write cycles The write cycle lasts one additional clock in this case This attribute is applicable to an internal QUICC master and to an external MC68030 QUICC 0 Reads and writes are the same length 1 Add one clock to write cycles for DRAM banks NOTE This bit must be set by the user if page mode is enabled for this DRAM bank PGME 1 and w...

Страница 8: ...nt on BACK40 On page 6 72 the description of the BACK40 for the zero case the following statement should be added The QUICC will assert TBI on an access to this memory area 17 Error in Note at TRLXQ On page 6 72 the 3rd note under TRLXQ Timing Relax User should avoid setting both TRLXQ and CSNTQ 1 when TCYC 0 This combination will result in a bus cycle without CS assertion is not correct and shoul...

Страница 9: ...tion 7 6 2 1 The STP bit in the ICCR was designed to conserve power when IDMA was not in use This function has been removed due to erratic behavior The user must keep this bit clear Bit 15 of ICCR is now reserved 3 Error in note On page 7 33 the note under section 7 6 3 Interface Signals should be as follows NOTE DREQ must be level sensitive if IDMA uses buffer chaining or auto buffer mode 4 Wrong...

Страница 10: ...nformation contained in the next buffer de scriptor Thus you should continually assert DREQ until you receive a DACK when using buffer chaining mode or auto buffer mode Also on page 7 43 the following paragraph should be added after point 3 4 You may not use cycle steal mode if you are using buffer chaining or auto buffer mode 8 Error in example On page 7 55 the third step in the buffer chaining e...

Страница 11: ...The correct acronym is FSD not SFD 14 Typo in SI Status Register On page 7 87 section 7 8 5 5 first paragraph second sentence The value of this register is valid only when the corresponding bit in the SIGMR is clear The acronym SIGMR should have been SICMR 15 Errata and missing note in GSMR On page 7 113 the note under the description of CDP was not clear and should be replaced with the following ...

Страница 12: ...ter the description of DRT bit User should set the preamble bit in the transmit buffer descriptor if the QUICC is being used in multi drop UART mode Also on page 7 158 the following note should be added after the description of SYN Synchronous Mode bit NOTE RINV bit in the GSMR must be cleared if synchronous UART mode is selected 20 Missing bits in HDLC mode register On page 7 178 the following bi...

Страница 13: ...s indicated below table should include bit 3 c RCH Receive Character text description should be removed 24 Missing Note on Ethernet Collision On Page 7 241 section 7 10 23 5 the following note should be added at the end of the third paragraph NOTE If an Ethernet frame is made up of multiple buffers the user should not reuse the first buffer descriptor until the last buffer de scriptor of the frame...

Страница 14: ...fficient and should be replaced with the following paragraph Once the TEN bit is set in SMCMR the SMC waits for the transmit FIFO to be loaded before attempting to achieve synchronization Once the transmit FIFO is loaded synchronization and transmission begin according to the following conditions If a buffer is made ready when the SMC is enabled then the first byte will be placed in time slot 1 if...

Страница 15: ... 2 Missing Word On Page 8 3 section 8 3 first paragraph third sentence The XTAL and XFC pins are associated with analog signals and are not included in the boundary scan register was missing the word EXTAL The sentence should be The EXTAL XTAL and XFC pins are associated with analog signals and are not included in the boundary scan register 3 Error in Pin Name On Page 8 6 Table 8 2 the pin name fo...

Страница 16: ...requirement in the application A 4 MHz crystal or a 32 768 kHz crystal could have been used if desired See section 6 5 for notes on crystal use The QUICC clocking section allows for the clock oscillator to be kept running through the VDDSYN pin in a power down situation This section does not address low power issues however 3 Typo on Configuring the Memory Controller On page 9 11 section 9 1 3 2 t...

Страница 17: ...gardless of chip select configuration 8 Error in Caching Sample Code On Page 9 53 section 9 5 4 correct the following in the code sample a MOVE L 003FC020 D0 should be changed to MOVE L 003FC040 D0 b MOVE L 403FC010 D0 should be changed to MOVE L 403FC020 D0 9 Error in Figure 9 33 1 Mbyte DRAM Bank 32 Bits Wide On Page 9 87 Figure 9 33 correct the following a On the first MC74F157 B0 B3 should be ...

Страница 18: ...l Outputs and I O Pins except TMS TDI and TRST Vin 0 5 2 4 V IOZ 2 5 2 5 µA Output Low Voltage For 3 3 volt part I OL 2 0 mAA31 A0 FC3 0 SIZ0 1 D31 D0 CLKO1 2 FREEZE IPIPE0 1 IFETCH BKPTO IOL 3 2 mA PA0 2 4 6 8 15 PB0 5 PB8 17 PC0 11 TDO PERR PRTY0 3 IOUT0 2 AVECO AS CAS3 0 BLCRO RAS0 7 IOL 5 3 mA DSACK0 1 R W DS OE RMC BG BGACK BERR IOL 7 mATXD1 4 IOL 8 9 mAPB6 PB7 HALT RESET BR Output VOL 0 5 0 ...

Страница 19: ...ASx Asserted On page 10 28 Table 10 10 specification 115 was printed incorrectly The correct spec is as follows 20 CLKO1 High to R W Low tCHRL 3 20 3 15 ns 20A CASx Low to R W Low Only in page mode and when the load capacitance is the same on CAS and R W Pin tCARL 0 0 ns 23 CLKO1 High to Data Out Valid tCHDO 23 18 ns 23A CLKO1 High to parity Valid tCHPV 25 20 ns Num Characteristic Symbol 3 3 V 5 0...

Страница 20: ...238 are not correct needed and should be deleted The Figures affected are 10 25 10 26 for 030 360 external masters and Figure 10 39 on page 10 50 for 040 external masters 13 Error in Figure On pages 10 34 and 10 35 the negation timing for BCLRO is not correct In both figures the negation of the signal BCLRO is shown to be at the rising edge of CLKO1 where BGACK is asserted The signal is instead ne...

Страница 21: ... released 2Q97 16 Typo on Figure 10 31 On page 10 42 Figure 10 31 specification 187 was referenced to the wrong place The cor rect reference should be from assertion of MBARE to assertion of DS 17 Typo on specification number On page 10 45 and page 10 47 the specification number for R W to AS assertion should be 214 not 164 18 Typo on External MC68030 MC68360 DRAM Asynchronous Cycle Timing Diagram...

Страница 22: ...w specification 22 Missing information and figures on MC68040 SRAM R W On page 10 57 the figure title should be replaced with the following Figure 10 44 a MC68040 EC040 SRAM Read Cycles TSS40 0 CSNT40 1 The following figure should be added after figure 10 44 a Num Characteristic 3 3 V or 5 0 V 5 0V Unit 25 0 MHz 33 34MHz Min Max Min Max 2881 Address Transfer Attributes Valid to EXTAL High TSS40 0 ...

Страница 23: ...is set to 1 The following figure should be added below figure 10 45 a CLKO1 OUTPUT TS INPUT A31 A0 INPUT TRANSFER ATTRIBUTES INPUT C1 C2 TA OUTPUT TBI OUTPUT CSx OUTPUT BADD3 BADD2 OUTPUT BKPTO OUTPUT OE OUTPUT READ CYCLES WE OUTPUT NOTE MC68040 Transfer Attribute Signals SIZx TTx TMx R W LOCK TEA INPUT 288 254 281 253 280 282 258 257 284 285 292 291 293 294 301 252 300 259 WRITE CYCLES 287 Freesc...

Страница 24: ...K DONE Asserted 3 24 3 18 ns 2 CLKO1 Low to DACK DONE Negated 3 24 3 18 ns C1 C2 CLKO1 OUTPUT TS INPUT A31 A0 INPUT TRANSFER ATTRIBUTES INPUT BADD3 BADD2 OUTPUT C3 BKPTO OUTPUT TEA INPUT CSn OUTPUT TA INPUT 251 280 252 253 254 281 289 290 300 301 285 284A TBI OUTPUT 258 TA OUTPUT 257 286 NOTE MC68040 Transfer Attribute Signals SIZx TTx TMx R W LOCK OE and WE are not supporrted when TSS40 is set to...

Страница 25: ... correct specification Section 11 ORDERING INFORMATION AND MECHANICAL DATA 1 Missing pin name for BGA On page 11 5 the pin name for pin R16 is missing This pin should be labeled NC 2 Typo on CQFP dimension On page 11 6 The specification for G should have been 0 197 BSC not 0 019 BSC Additional Information 1 Initialize the Dual port ram After Reset the dual port ram of the QUICC will come up at ran...

Страница 26: ...ing bit 5 in the CLKOCR will disable loss of lock resets 3 Phase Lock Loop The following section describes the performance guidelines for the on chip phase locked loop on the QUICC The following explanations should be considered as general observations on expected PLL behavior and should not be considered as specifications The parts are not tested to verify these exact numbers These observations w...

Страница 27: ...ong time then the allowed jitter can be 2 The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values 8 K Factor for A C Specification The following numbers should be used to estimate derating of load capacitance a K factor for decreasing load less then 100pf 0 2 ns 10Pf b K factor for increasing load more then 100pf 0 6 ns 10pf 9 Low Fr...

Страница 28: ...l speed oscillator which is then fanned out to each QUICC possibly via buffers or a PLL The use of CLKO1 output of one QUICC to be the input clock of other QUICC s is not recommended When using a crystal the CLKO1 output does not meet the jitter requirements of the EXTAL input Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

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